IP Library Assignment 038039/0328
Patent Assignment
Reel/Frame 038039/0328

Merger

Recorded: 2016-03-08 Pages: 6
Assignor
XPLIANT, INC.
Executed: 2015-04-29
Assignee
CAVIUM NETWORKS LLC
2315 N. FIRST STREET, SAN JOSE, CALIFORNIA, 95131
Covered Properties (58)
System for and Method of Combining Cmos Inverters of Multiple Drive Strengths to Create Tune-Able Clock Inverters of Variable Drive Strengths in Hybrid Tree-Mesh Clock Distribution Networks
Patent: 9,390,209 →
Application: 14/141,076 →
Publication: US 2015/0186560
System for and Method of Placing Clock Stations Using Variable Drive-Strength Clock Drivers Built Out of a Smaller Subset of Base Cells for Hybrid Tree-Mesh Clock Distribution Networks
Patent: 9,443,053 →
Application: 14/141,096 →
Publication: US 2015/0186589
Matrix of on-Chip Routers Interconnecting a Plurality of Processing Engines and a Method of Routing Using Thereof
Patent: 9,548,945 →
Application: 14/142,497 →
Publication: US 2015/0188848
Method and System for Reconfigurable Parallel Lookups Using Multiple Shared Memories
Patent: 9,620,213 →
Application: 14/142,511 →
Publication: US 2015/0187419
Method and Apparatus for Parallel and Conditional Data Manipulation in a Software-Defined Network Processing Engine
Patent: 9,880,844 →
Application: 14/144,260 →
Publication: US 2015/0186143
Apparatus and Method of Generating Lookups and Making Decisions for Packet Modifying and Forwarding in a Software-Defined Network Engine
Patent: 9,379,963 →
Application: 14/144,270 →
Publication: US 2015/0186516
Method and Apparatus for Analytics in a Network Switch
Application: 14/289,533 →
Publication: US 2015/0350089
Method and Apparatus for Table Aging in a Network Switch
Patent: 9,773,036 →
Application: 14/289,548 →
Publication: US 2015/0347313
Counter with Overflow Fifo and a Method Thereof
Application: 14/302,343 →
Publication: US 2015/0365339
Hierarchical Statistically Multiplexed Counters and a Method Therof
Patent: 9,413,357 →
Application: 14/302,351 →
Publication: US 2015/0365355
Method of Modifying Packets to a Generic Format for Enabling Programmable Modifications and an Apparatus Thereof
Patent: 9,961,167 →
Application: 14/309,603 →
Publication: US 2015/0373155
Method of Representing a Generic Format Header Using Continuous Bytes and an Apparatus Thereof
Patent: 9,473,601 →
Application: 14/309,619 →
Publication: US 2015/0373169
Method of Using a Unique Packet Identifier to Identify Structure of a Packet and an Apparatus Thereof
Patent: 9,497,294 →
Application: 14/309,633 →
Publication: US 2015/0373156
Method of Using Generic Modification Instructions to Enable Flexible Modifications of Packets and an Apparatus Thereof
Patent: 9,531,848 →
Application: 14/309,650 →
Publication: US 2015/0373159
Method of Using Bit Vectors to Allow Expansion and Collapse of Header Layers Within Packets for Enabling Flexible Modifications and an Apparatus Thereof
Patent: 9,635,146 →
Application: 14/309,659 →
Publication: US 2015/0373160
Method of Splitting a Packet into Individual Layers for Modification and Intelligently Stitching Layers Back Together After Modification and an Apparatus Thereof
Patent: 9,531,849 →
Application: 14/309,679 →
Publication: US 2015/0373161
Leaky Bucket Model to Mimic Behavior of a Mac and a Method Thereof
Application: 14/309,700 →
Publication: US 2015/0372926
Method of Extracting Data from Packets and an Apparatus Thereof
Patent: 9,516,145 →
Application: 14/309,726 →
Publication: US 2015/0373163
Method of Forming a Hash Input from Packet Contents and an Apparatus Thereof
Patent: 9,438,703 →
Application: 14/309,739 →
Publication: US 2015/0373164
Method of Handling Large Protocol Layers for Configurable Extraction of Layer Information and an Apparatus Thereof
Application: 14/309,763 →
Publication: US 2015/0373165
Method of Reducing Latency in a Flexible Parser and an Apparatus Thereof
Application: 14/309,773 →
Publication: US 2015/0372860
Method of Dynamically Renumbering Ports and an Apparatus Thereof
Patent: 9,742,694 →
Application: 14/309,789 →
Publication: US 2015/0372864
Method of Identifying Internal Destinations of Network Packets and an Apparatus Thereof
Patent: 9,628,385 →
Application: 14/309,802 →
Publication: US 2015/0373166
Network Device, System and Method Having a Rotated Chip Floorplan
Application: 14/331,099 →
Publication: US 2016/0014885
Baseboard Interconnection Device, System and Method
Application: 14/331,105 →
Publication: US 2016/0012006
Hierarchical Hardware Linked List Approach for Multicast Replication Engine in a Network Asic
Patent: 9,813,327 →
Application: 14/494,168 →
Publication: US 2016/0087809
Fast Hardware Switchover in a Control Path in a Network Asic
Patent: 9,729,338 →
Application: 14/494,187 →
Publication: US 2016/0087808
Session Based Packet Mirroring in a Network Asic
Patent: 9,760,418 →
Application: 14/494,229 →
Publication: US 2016/0085475
Multicast Replication Engine of a Network Asic and Methods Thereof
Patent: 9,565,136 →
Application: 14/494,291 →
Publication: US 2016/0085644
Apparatus and a Method of Detecting Errors on Registers
Application: 14/521,333 →
Publication: US 2016/0117217
Two Modes of a Configuration Interface of a Network Asic
Patent: 9,990,324 →
Application: 14/521,354 →
Publication: US 2016/0117282
Smart Holding Registers to Enable Multiple Register Accesses
Patent: 9,542,342 →
Application: 14/521,359 →
Publication: US 2016/0117271
Multiple-Interrupt Propagation Scheme in a Network Asic
Application: 14/521,367 →
Publication: US 2016/0117273
Hybrid Wildcard Match Table
Application: 14/536,937 →
Publication: US 2016/0134536
Packet Processor Forwarding Database Cache
Application: 14/667,488 →
Publication: US 2016/0285990
Phantom Queue Link Level Load Balancing System, Method and Device
Patent: 9,900,253 →
Application: 14/667,568 →
Publication: US 2016/0065477
Co-Verification - of Hardware and Software, a Unified Approach in Verification
Patent: 9,372,772 →
Application: 14/671,993 →
Software Assisted Hardware Configuration for Software Defined Network System-On-Chip
Application: 14/672,006 →
Publication: US 2016/0283413
Packet Tracking in a Verification Environment
Application: 14/672,016 →
Publication: US 2016/0142280
Testbench Builder, System, Device and Method Including Latency Detection
Patent: 9,817,067 →
Application: 14/672,025 →
Publication: US 2016/0139202
Packet Memory System, Method and Device for Preventing Underrun
Application: 14/673,807 →
Publication: US 2016/0294729
Packet Processing System, Method and Device to Optimize Packet Buffer Space
Patent: 9,747,226 →
Application: 14/673,813 →
Publication: US 2016/0292096
Packet Processing System, Method and Device Having Reduced Static Power Consumption
Application: 14/673,819 →
Publication: US 2016/0292079
Packet Processing System, Method and Device Utilizing a Port Client Chain
Patent: 9,606,942 →
Application: 14/673,828 →
Publication: US 2016/0292091
Packet Processing System, Method and Device Utilizing Memory Sharing
Patent: 9,582,215 →
Application: 14/673,835 →
Publication: US 2016/0291895
Control Path Subsystem, Method and Device Utilizing Memory Sharing
Patent: 9,612,950 →
Application: 14/673,836 →
Publication: US 2016/0292070
Datapath Subsystem, Method and Device Utilizing Memory Sharing
Patent: 9,652,171 →
Application: 14/673,840 →
Publication: US 2016/0291896
Parser Engine Programming Tool for Programmable Network Devices
Patent: 9,606,781 →
Application: 14/675,667 →
Publication: US 2016/0139892
Code Processor to Build Orthogonal Execution Blocks for Programmable Network Devices
Patent: 9,864,582 →
Application: 14/675,674 →
Publication: US 2016/0139893
Algorithm to Achieve Optimal Layout of Decision Logic Elements for Programmable Network Devices
Patent: 9,582,251 →
Application: 14/675,682 →
Publication: US 2016/0139900
Algorithm to Derive Logic Expression to Select Execution Blocks for Programmable Network Devices
Patent: 9,864,583 →
Application: 14/675,692 →
Publication: US 2016/0139896
Algorithm to Achieve Optimal Layout of Instruction Tables for Programmable Network Devices
Patent: 9,870,204 →
Application: 14/675,696 →
Publication: US 2016/0139898
Code Generator for Programmable Network Devices
Patent: 9,864,584 →
Application: 14/675,702 →
Publication: US 2016/0139887
Compiler Architecture for Programmable Application Specific Integrated Circuit Based Network Devices
Patent: 9,836,283 →
Application: 14/675,710 →
Publication: US 2016/0139891
Barrel Compactor System, Method and Device
Patent: 9,954,551 →
Application: 14/675,728 →
Publication: US 2016/0294408
Barrel Compactor System, Method and Device Having Cell Combination Logic
Patent: 9,584,635 →
Application: 14/675,734 →
Publication: US 2016/0294988
Policer Architecture
Patent: 9,871,733 →
Application: 14/676,679 →
Publication: US 2016/0142322
Hybrid Wildcard Match Table
Application: 14/932,791 →
Publication: US 2016/0134537
Related Assignments (24)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Apr 15, 2014
From: TRAN, ANH T.; SCHMIDT, GERALD; DANIEL, TSAHI; BALAN, MOHAN
To: XPLIANT, INC.
Reel/Frame 032681/0134 →
Assignment of Assignor's Interest Apr 15, 2014
From: TRAN, ANH T.; SCHMIDT, GERALD; DANIEL, TSAHI; KRISHNAMOORTHY, HARISH
To: XPLIANT, INC.
Reel/Frame 032681/0176 →
Assignment of Assignor's Interest Apr 15, 2014
From: TRAN, ANH T.; SCHMIDT, GERALD; DANIEL, TSAHI; SHRIVASTAVA, SAURABH
To: XPLIANT, INC.
Reel/Frame 032681/0165 →
Assignment of Assignor's Interest Apr 15, 2014
From: TRAN, ANH T.; SCHMIDT, GERALD; DANIEL, TSAHI; SIVA, NIMALAN
To: XPLIANT, INC.
Reel/Frame 032681/0139 →
Assignment of Assignor's Interest Apr 15, 2014
From: JAYAKUMAR, NIKHIL; TRIVEDI, VIVEK; PALISETTI, VASANT K.; MULA, BHAGAVATI R.
To: XPLIANT, INC.
Reel/Frame 032681/0040 →
Assignment of Assignor's Interest Apr 15, 2014
From: JAYAKUMAR, NIKHIL; TRIVEDI, VIVEK; PALISETTI, VASANT K.; MULA, BHAGAVATI R.
To: XPLIANT, INC.
Reel/Frame 032681/0079 →
Assignment of Assignor's Interest Jul 10, 2014
From: SINGH, CHIRINJEEV; DESAI, VANDANA
To: XPLIANT, INC.
Reel/Frame 033291/0502 →
Assignment of Assignor's Interest Jul 10, 2014
From: SINGH, CHIRINJEEV; DANIEL, TSAHI; SCHMIDT, GERALD; PATEL, SAURIN
To: XPLIANT, INC.
Reel/Frame 033291/0459 →
Assignment of Assignor's Interest Jul 10, 2014
From: SINGH, CHIRINJEEV; DANIEL, TSAHI; SCHMIDT, GERALD; PATEL, SAURIN
To: XPLIANT, INC.
Reel/Frame 033291/0476 →
Assignment of Assignor's Interest Jul 10, 2014
From: ANAND, VISHAL; DANIEL, TSAHI; SCHMIDT, GERALD
To: XPLIANT, INC.
Reel/Frame 033291/0515 →
Assignment of Assignor's Interest Jul 10, 2014
From: WANG, WEIHUANG; SCHMIDT, GERALD; DANIEL, TSAHI; SHRIVASTAVA, SAURABH
To: XPLIANT, INC.
Reel/Frame 033286/0294 →
Assignment of Assignor's Interest Jul 10, 2014
From: WANG, WEIHUANG; SCHMIDT, GERALD; DANIEL, TSAHI; BALAN, MOHAN
To: XPLIANT, INC.
Reel/Frame 033286/0450 →
Assignment of Assignor's Interest Jul 10, 2014
From: WANG, WEIHUANG; ATLURI, SRINATH
To: XPLIANT, INC.
Reel/Frame 033286/0658 →
Assignment of Assignor's Interest Jul 10, 2014
From: WANG, WEIHUANG; SCHMIDT, GERALD; ATLURI, SRINATH; MA, WEINAN
To: XPLIANT, INC.
Reel/Frame 033286/0915 →
Assignment of Assignor's Interest Jul 10, 2014
From: SINGH, CHIRINJEEV; ANAND, VISHAL; DANIEL, TSAHI; SCHMIDT, GERALD
To: XPLIANT, INC.
Reel/Frame 033288/0312 →
Assignment of Assignor's Interest Jul 10, 2014
From: SINGH, CHIRINJEEV; DANIEL, TSAHI; SCHMIDT, GERALD
To: XPLIANT, INC.
Reel/Frame 033288/0453 →
Assignment of Assignor's Interest Jul 10, 2014
From: SINGH, CHIRINJEEV; ANAND, VISHAL
To: XPLIANT, INC.
Reel/Frame 033291/0380 →
Assignment of Assignor's Interest Jul 10, 2014
From: SINGH, CHIRINJEEV; DANIEL, TSAHI; SCHMIDT, GERALD; PATEL, SAURIN
To: XPLIANT, INC.
Reel/Frame 033291/0422 →
Assignment of Assignor's Interest Mar 8, 2016
From: CAVIUM NETWORKS LLC
To: CAVIUM, INC.
Reel/Frame 038040/0251 →
Security Agreement Aug 17, 2016
From: CAVIUM, INC.; CAVIUM NETWORKS LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039715/0449 →
Release of Security Interest Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
Change of Name Sep 27, 2018
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 047577/0653 →
Assignment of Assignor's Interest Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
Assignment of Assignor's Interest May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →