MANAGING INSTRUCTION ORDER IN A PROCESSOR PIPELINE

1 . A method for executing instructions in a processor, the method comprising:

determining identifiers corresponding to instructions in at least one decode stage of a pipeline of the processor, with a set of identifiers for at least one instruction including:

at least one operation identifier identifying an operation to be performed by the instruction,

at least one storage identifier identifying a storage location for storing an operand of the operation, and

at least one storage identifier identifying a storage location for storing a result of the operation; and

assigning a multi-dimensional identifier to at least one storage identifier.

2 . The method of claim 1 , wherein assigning a multi-dimensional identifier to a first storage identifier includes:

assigning a first dimension of the multi-dimensional identifier to a value corresponding to the first storage identifier, and

assigning a second dimension of the multi-dimensional identifier to a value indicating one of a plurality of sets of physical storage locations.

3 . The method of claim 1 , further comprising selecting a plurality of instructions to be issued to one or more stages of the pipeline in which multiple sequences of instructions are executed in parallel through separate paths through the pipeline, based at least in part on a Boolean value provided by circuitry that applies logic to condition information stored in the processor representing conditions for multiple instructions in the set.

4 . The method of claim 3 , wherein the condition information comprises one or more scoreboard tables.

5 . The method of claim 3 , further comprising classifying, in at least one stage of the pipeline, operations to be performed by instructions, the classifying including:

classifying a first set of operations as operations for which out-of-order execution is allowed, and

classifying a second set of operations as operations for which out-of-order execution with respect to one or more specified operations is not allowed, the second set of operations including at least store operations.

6 . The method of claim 3 , further comprising selecting results of instructions executed out-of-order to commit the selected results in-order, the selecting including, for a first result of a first instruction and a second result of a second instruction executed before and out-of-order relative to the first instruction:

determining which stage of the pipeline stores the second result, and

committing the first result directly from the determined stage over a forwarding path, before committing the second result.

7 . The method of claim 1 , further comprising classifying, in at least one stage of the pipeline, operations to be performed by instructions, the classifying including:

classifying a first set of operations as operations for which out-of-order execution is allowed, and

classifying a second set of operations as operations for which out-of-order execution with respect to one or more specified operations is not allowed, the second set of operations including at least store operations.

8 . The method of claim 1 , further comprising selecting results of instructions executed out-of-order to commit the selected results in-order, the selecting including, for a first result of a first instruction and a second result of a second instruction executed before and out-of-order relative to the first instruction:

determining which stage of the pipeline stores the second result, and

committing the first result directly from the determined stage over a forwarding path, before committing the second result.

9 . A processor, comprising:

circuitry in at least one decode stage of a pipeline of the processor configured to

determine identifiers corresponding to instructions, with a set of identifiers for at least one instruction including:

at least one operation identifier identifying an operation to be performed by the instruction,

at least one storage identifier identifying a storage location for storing an operand of the operation, and

at least one storage identifier identifying a storage location for storing a result of the operation; and

circuitry configured to assign a multi-dimensional identifier to at least one storage identifier.

10 . The processor of claim 9 , wherein assigning a multi-dimensional identifier to a first storage identifier includes:

assigning a first dimension of the multi-dimensional identifier to a value corresponding to the first storage identifier, and

assigning a second dimension of the multi-dimensional identifier to a value indicating one of a plurality of sets of physical storage locations.

11 . The processor of claim 9 , further comprising circuitry configured to select a plurality of instructions to be issued to one or more stages of the pipeline in which multiple sequences of instructions are executed in parallel through separate paths through the pipeline, based at least in part on a Boolean value provided by circuitry that applies logic to condition information stored in the processor representing conditions for multiple instructions in the set.

12 . The processor of claim 11 , wherein the condition information comprises one or more scoreboard tables.

13 . The processor of claim 11 , further comprising circuitry in at least one stage of the pipeline configured to classify operations to be performed by instructions, the classifying including:

classifying a first set of operations as operations for which out-of-order execution is allowed, and

classifying a second set of operations as operations for which out-of-order execution with respect to one or more specified operations is not allowed, the second set of operations including at least store operations.

14 . The processor of claim 11 , further comprising circuitry configured to select results of instructions executed out-of-order to commit the selected results in-order, the selecting including, for a first result of a first instruction and a second result of a second instruction executed before and out-of-order relative to the first instruction:

determining which stage of the pipeline stores the second result, and

committing the first result directly from the determined stage over a forwarding path, before committing the second result.

15 . The processor of claim 9 , further comprising circuitry in at least one stage of the pipeline configured to classify operations to be performed by instructions, the classifying including:

classifying a first set of operations as operations for which out-of-order execution is allowed, and

classifying a second set of operations as operations for which out-of-order execution with respect to one or more specified operations is not allowed, the second set of operations including at least store operations.

16 . The processor of claim 9 , further comprising circuitry configured to select results of instructions executed out-of-order to commit the selected results in-order, the selecting including, for a first result of a first instruction and a second result of a second instruction executed before and out-of-order relative to the first instruction:

determining which stage of the pipeline stores the second result, and

committing the first result directly from the determined stage over a forwarding path, before committing the second result.