Packet traffic control in a network processor
View Patent ↗A network processor controls packet traffic in a network by maintaining a count of pending packets. In the network processor, a pipe identifier (ID) is assigned to each of a number of paths connecting a packet output to respective network interfaces receiving those packets. A corresponding pipe ID is attached to each packet as it is transmitted. A counter employs the pipe ID to maintain a count of packets to be transmitted by a network interface. As a result, the network processor manages traffic on a per-pipe ID basis to ensure that traffic thresholds are not exceeded.
1. A system for controlling packet traffic in a network, comprising:
a plurality of network interfaces configured to transmit packets to a plurality of receivers across a network;
a control circuit configured to select the packets for forwarding to the plurality of network interfaces, the control circuit attaching a pipe identifier (ID) to each of the packets, the pipe ID indicating an internal path connecting the control circuit to one of the plurality of network interfaces through which the packet is to be transmitted, the internal path being one of a plurality of internal paths, each of the plurality of internal paths connecting the control circuit to a respective one of the plurality of network interfaces; and
a counter configured to maintain a count of packets to be transmitted by each network interface per pipe ID, the counter comparing the count against a threshold and providing an indication to the control circuit in response to the count exceeding the threshold, the counter updating the count based on a count update message provided by the control circuit, the count update message including the pipe ID and a word count indicating a data size of the packet;
wherein the control circuit, in response to the indication from the counter, limits packet traffic through the internal path associated with the pipe ID and refrains from scheduling further packet for transmittal through the internal path.
2. The system of claim 1 , wherein the control circuit is further configured to limit packet traffic through one of the paths in response to receiving a backpressure command from one of the plurality of receivers.
3. The system of claim 1 , wherein the counter is further configured to maintain a count of bytes of the packets to be transmitted by the network interface per pipe ID, the counter comparing the count of bytes against a byte threshold and providing a second indication to the control circuit in response to the count of bytes exceeding the threshold.
4. The system of claim 3 , wherein the control circuit, in response to the second indication from the counter, limits packet traffic through the path associated with the pipe ID.
5. The system of claim 1 , wherein the path includes a port at the control circuit and a channel connecting one of the plurality of network interfaces to one of the plurality of receivers.
6. The system of claim 1 , wherein the counter is configured to increment a value in response to the control circuit scheduling one of the packets for transmittal to one of the plurality of network interfaces, the value being associated with the packet ID of the packet.
7. The system of claim 6 , wherein the counter is configured to decrement the value in response to the network interface transmitting the packet to the receiver.
8. The system of claim 1 , wherein the counter is configured to maintain an additional count of packets to be transmitted by each network interface, the additional count being specific to an individual one of the plurality of network interfaces.
9. The system of claim 8 , wherein the counter compares the additional count against a threshold and providing an indication to the control circuit in response to the count exceeding the threshold.
10. The system of claim 1 , wherein the counter maintains the count based on a status of a plurality of buffers at each of the plurality of network interfaces, each of the plurality of buffers being associated with a path.
11. The system of claim 1 , wherein the counter maintains the count based on a status of a plurality of buffers at the control circuit, each of the plurality of buffers being associated with a path.