Flexible instruction execution in a processor pipeline
View Patent ↗Executing instructions in a processor includes analyzing operations to be performed by instructions, including: determining a latency associated with a first operation to be performed by a first instruction, determining a second operation to be performed by a second instruction, where a result of the second operation depends on a result of the first operation, and assigning a value to the second instruction corresponding to the determined latency associated with the first operation. One or more instructions are selected to be issued together in the same clock cycle of the processor from among instructions whose operations have been analyzed, the selected instructions occurring consecutively according to a program order. A start of execution of the second instruction is delayed by a particular number of clock cycles after the clock cycle in which the second instruction is issued according to the value assigned to the second instruction.
1. A method for executing instructions in a processor, the method comprising:
analyzing, in at least one stage of a pipeline of the processor, operations to be performed by instructions, the analyzing including:
determining a latency associated with a first operation to be performed by a first instruction,
determining a second operation to be performed by a second instruction, where a result of the second operation depends on a result of the first operation, and
assigning a value to the second instruction corresponding to the determined latency associated with the first operation;
selecting one or more instructions to be issued together in the same clock cycle of the processor from among a plurality of instructions whose operations have been analyzed, the selected one or more instructions occurring consecutively according to a program order; and
executing instructions that have been issued, through multiple execution stages of the pipeline, and delaying a start of execution of the second instruction by a particular number of clock cycles after the clock cycle in which the second instruction is issued according to the value assigned to the second instruction.
2. The method of claim 1 , wherein any instruction selected to be issued in a clock cycle after a clock cycle in which a previous instruction issued occurs later in the program order than the previous instruction.
3. The method of claim 2 , wherein the first instruction and the second instruction are selected to be issued together in a first clock cycle.
4. The method of claim 3 , wherein a third instruction is selected to be issued in a clock cycle after the first clock cycle, and a start of execution of the third instruction occurs before the start of execution of the second instruction.
5. The method of claim 4 , wherein there are multiple paths through the execution stages, and the third instruction is executed along a different path than the second instruction.
6. The method of claim 1 , wherein there are multiple paths through the execution stages, and the second instruction is executed along a different path than the first instruction.
7. The method of claim 1 , wherein there are multiple paths through the execution stages, and at least one instruction assigned a value is executed along a first path and at least one instruction assigned a value is executed along a second path different from the first path.
8. The method of claim 1 , wherein the result of the second operation is sent from a first execution stage to a second execution stage during a clock cycle, and there is at least one execution stage between the first and second execution stages over which the result of the second instruction skips.
9. The method of claim 8 , wherein the number of execution stages over which the result of the second instruction skips is determined based on the value assigned to the second instruction.
10. The method of claim 9 , wherein the number of execution stages over which the result of the second instruction skips is equal to the value assigned to the second instruction.
11. A processor comprising:
at least one stage of a pipeline of the processor including circuitry configured to analyze operations to be performed by instructions, the analyzing including:
determining a latency associated with a first operation to be performed by a first instruction,
determining a second operation to be performed by a second instruction, where a result of the second operation depends on a result of the first operation, and
assigning a value to the second instruction corresponding to the determined latency associated with the first operation;
circuitry configured to select one or more instructions to be issued together in the same clock cycle of the processor from among a plurality of instructions whose operations have been analyzed, the selected one or more instructions occurring consecutively according to a program order; and
circuitry configured to execute instructions that have been issued, through multiple execution stages of the pipeline, and delay a start of execution of the second instruction by a particular number of clock cycles after the clock cycle in which the second instruction is issued according to the value assigned to the second instruction.
12. The processor of claim 11 , wherein any instruction selected to be issued in a clock cycle after a clock cycle in which a previous instruction issued occurs later in the program order than the previous instruction.
13. The processor of claim 12 , wherein the first instruction and the second instruction are selected to be issued together in a first clock cycle.
14. The processor of claim 13 , wherein a third instruction is selected to be issued in a clock cycle after the first clock cycle, and a start of execution of the third instruction occurs before the start of execution of the second instruction.
15. The processor of claim 14 , wherein there are multiple paths through the execution stages, and the third instruction is executed along a different path than the second instruction.
16. The processor of claim 11 , wherein there are multiple paths through the execution stages, and the second instruction is executed along a different path than the first instruction.
17. The processor of claim 11 , wherein there are multiple paths through the execution stages, and at least one instruction assigned a value is executed along a first path and at least one instruction assigned a value is executed along a second path different from the first path.
18. The processor of claim 11 , wherein the result of the second operation is sent from a first execution stage to a second execution stage during a clock cycle, and there is at least one execution stage between the first and second execution stages over which the result of the second instruction skips.
19. The processor of claim 18 , wherein the number of execution stages over which the result of the second instruction skips is determined based on the value assigned to the second instruction.
20. The processor of claim 19 , wherein the number of execution stages over which the result of the second instruction skips is equal to the value assigned to the second instruction.