Method and apparatus for managing write back cache
View Patent ↗A network services processor includes an input/output bridge that avoids unnecessary updates to memory when cache blocks storing processed packet data are no longer required. The input/output bridge monitors requests to free buffers in memory received from cores and IO units in the network services processor. Instead of writing the cache block back to the buffer in memory that will be freed, the input/output bridge issues don't write back commands to a cache controller to clear the dirty bit for the selected cache block, thus avoiding wasteful write-backs from cache to memory. After the dirty bit is cleared, the buffer in memory is freed, that is, made available for allocation to store data for another packet.
1. A network services processor comprising:
a plurality of processors;
a coherent shared memory including a cache and a memory, the coherent shared memory shared by the plurality of processors;
a free pool allocator configured to maintain pools of pointers to free memory locations;
an input/output bridge coupled to the plurality of processors and the cache, the input/output bridge intercepting memory free commands issued by one or more of the processors and destined for the free pool allocator, each memory free command requesting to free one or more portions in the memory, and based on intercepting a memory free command to request to free a selected memory portion, issuing a don't write back command to a cache controller, and forwarding the memory free command to the free pool allocator based on completion of the don't write back command; and
the cache controller coupled to the plurality of processors, the cache and the input/output bridge, the cache controller configured to receive the don't write back command from the input/output bridge and to compare an address of the selected memory portion to addresses stored in the cache and, in an event the address of the selected memory portion is replicated in the cache, void a memory update to the selected memory portion by clearing a dirty bit associated with a corresponding modified cache block.
2. The network services processor of claim 1 wherein the input/output bridge further comprises:
a don't write back queue which stores don't write back commands to be issued to the cache controller.
3. The network services processor of claim 2 wherein the input/output bridge further comprises:
a free queue that stores memory free commands to free blocks to be added to a free pool.
4. The network services processor of claim 3 further comprising:
a plurality of processing units coupled to the input/output bridge, the input/output bridge storing packets to be transferred between processing units and the coherent shared memory in which packets are stored for processing by the processors.
5. The network services processor of claim 1 , wherein:
the free pool allocator further provides free lists of buffers in memory for storing received packets.
6. The network services processor of claim 1 , wherein the coherent shared memory is coupled to the processors and input/output bridge by a coherent memory bus that includes a commit bus, a store bus, a fill bus and an add bus.
7. A method comprising:
sharing a coherent shared memory among a plurality of processors, the coherent shared memory including a cache and a memory; and
intercepting, at an input/output bridge, memory free commands issued by one or more of the processors and destined for a free pool allocator configured to maintain pools of pointers to free memory locations, each memory free command requesting to free one or more portions in the memory and based on intercepting a memory free command to request to free a selected memory portion, issuing a don't write back command to a cache controller and forwarding the memory free command to the free pool allocator based on completion of the don't write back command; and
receiving, at a cache controller, the don't write back command from the input/output bridge and comparing an address of the selected memory portion to addresses stored in the cache and, in an event the address of the selected memory portion is replicated in the cache, voiding a memory update to the selected memory portion by clearing a dirty bit associated with a corresponding modified cache block.
8. The method of claim 7 further comprising:
storing don't write back commands to be issued to the cache controller in a don't write back queue.
9. The method of claim 7 further comprising:
storing memory free commands to free blocks to be added to a free pool in a free queue.
10. The method of claim 7 further comprising:
storing packets to be transferred between a plurality of processing units and the coherent shared memory in which packets are stored for processing by the processors.
11. The method of claim 7 , further comprising:
providing a list of free buffers in memory for storing received packets.
12. The method of claim 7 , wherein the coherent shared memory is coupled to the processors and input/output bridge by a coherent memory bus that includes a commit bus, a store bus, a fill bus and an add bus.