Method and apparatus for efficient determination of status from DMA lists
View Patent ↗Preferred embodiments of the present invention increase the efficiency of access to a constructed list of memory locations, or DMA list by a host processor. In order to circumvent the problem of latency between an I/O device and the host processor, preferred embodiments of the present invention store a copy of the DMA head pointer in the system memory, as well as on the I/O device. When the head pointer data is changed on the I/O device, the I/O device will use DMA to write the updated head pointer back to system memory.
1. A method performed in a system having an input/output device connected to a host system, comprising:
a) constructing, by the host system, a direct memory access list, having a head pointer, within a system memory of the host system; wherein the direct memory access list includes information regarding a plurality of direct memory access operations;
b) writing, by the host system, said direct memory access list and the head pointer into a memory of the input/output device;
c) updating, by the input/output device, the head pointer of the direct memory access list after a direct memory access operation is complete, the updated head pointer being stored on the input/output device;
d) duplicating, by the input/output device, the updated head pointer into the system memory of the host system;
e) determining, by the host system, when the updated head pointer is duplicated into system memory; and
f) accessing, by the host system, data stored in the system memory as a result of the direct memory access operation in response to the determination that the updated head pointer has been duplicated.
2. The method of claim 1 , wherein the duplication of the head pointer occurs after a read operation.
3. The method of claim 1 , wherein the duplication of the head pointer occurs after a write operation.
4. The method of claim 1 , wherein the duplication of the head pointer by the input/output device is accomplished by using a direct memory access operation.
5. The method of claim 1 , wherein the host system and input/output device are connected via a bus whose data access time is slower than access time for the host system to access system memory.
6. The method of claim 1 , further comprising:
determining, by the host system, that a successful data write operation has occurred, the determination made in response to the determination that the updated head pointer has been duplicated.
7. A method performed in a system having an input/output device connected to a host system, comprising:
(a) constructing a direct memory access list, having a head pointer, within a system memory of a host system; wherein the host system constructs the direct memory access list that includes information regarding a plurality of direct memory access operations;
(b) writing, by the host system, said direct memory access list and the head pointer into a memory of the input/output device;
(c) updating, by the input/output device, the head pointer of the direct memory access list after a direct memory access operation is complete, the updated head pointer being stored on the input/output device;
(d) duplicating, by the input/output device, the updated head pointer into the system memory of the host system;
(e) determining, by the host system, when the updated head pointer is duplicated into system memory; and
(f) determining, by the host system, that a successful data write operation has occurred, the determination made in response to the determination that the updated head pointer has been duplicated.
8. The method of claim 7 , wherein the duplication of the head pointer occurs after a read operation.
9. The method of claim 7 , wherein the duplication of the head pointer by the input/output device is accomplished by using a direct memory access operation.
10. The method of claim 7 , wherein the host system and input/output device are connected via a bus whose data access time is slower than access time for the host system to access system memory.
11. A system, comprising:
a host system having a processor and a system memory; and
an input/output device operationally coupled to the host system via a bus;
wherein the processor (a) constructs a direct memory access (DMA) list, having a head pointer; (b) stores the DMA list having information regarding a plurality of DMA operations and the header pointer within the system memory; (c) writes the DMA list and the head pointer into a memory of the input/output device; and
wherein the input/output device: (i) updates the DMA list and the head pointer after a direct memory access operation is completed; (ii) stores the updated head pointer at the input/output device; and (iii) duplicates the updated head pointer into the system memory of the host system; and
wherein the processor determines when the updated head pointer is duplicated into system memory; and accesses data stored in the system memory as a result of the DMA operation in response to the determination that the updated head pointer has been duplicated.
12. The system of claim 11 , wherein the duplication of the head pointer occurs after a read operation.
13. The system of claim 11 , wherein the updated head pointer is duplicated by the input/output device using a direct memory access operation.
14. The method of claim 11 , wherein the bus data access time is slower than access time for the host system to access system memory.