Clock distribution circuit with distributed delay locked loop
View Patent ↗In an embodiment, a clock distribution circuit includes a global delay locked loop (DLL) configured to receive a global clock input signal (RCLK), a lead/lag input signal and to output a clock signal. The circuit includes a plurality of clock distribution blocks, each clock distribution block configured to receive the output of the global DLL, a lead/lag signal and to output a leaf node clock signal, each clock distribution block further comprises a local DLL. The global DLL is further configured to align one of the leaf node clock signals to a reference clock based on its lead/lag input signal. Each clock distribution block is further configured to align its leaf node clock signal to a reference clock based on its lead/lag signal.
1. A clock distribution circuit comprising:
a global delay locked loop (DLL) configured to receive a global clock input signal, a lead/lag input signal and to output a clock signal;
a plurality of clock distribution blocks, each clock distribution block configured to receive the output of the global DLL, a lead/lag input signal and to output a leaf node clock signal, wherein each clock distribution block further comprises a local DLL;
wherein the global DLL is further configured to align one of the plurality of leaf node clock signals, output by one of the plurality of clock distribution blocks, to a reference clock, the lead/lag input signal of the global DLL connected to the lead/lag input signal of the one of the plurality of clock distribution blocks;
wherein each clock distribution block is further configured to align its leaf node clock signal to the reference clock based on its lead/lag input signal.
2. The clock distribution circuit of claim 1 , wherein an initial phase mismatch between any two leaf node clock signals is less than a phase of the global clock input signal.
3. The clock distribution circuit of claim 1 , wherein the global DLL is locked once it aligns one of the plurality of leaf node clock signals to the reference clock and no longer responds to its lead/lag input signal.
4. The clock distribution circuit of claim 1 , wherein the reference clock frequency is equal to or an integer sub-multiple of the global clock frequency.
5. The clock distribution circuit of claim 1 , wherein each local DLL further comprises a state machine configured to align an input clock signal to the reference clock based on at least its lead/lag input signal.
6. The clock distribution circuit of claim 5 , wherein the state machine of the local DLL is configured to transition from an initial state to a selected state based on at least its lead/lag input signal.
7. The clock distribution circuit of claim 1 , wherein the global DLL further comprises a state machine configured to align an input clock signal to the reference clock based on at least its lead/lag input signal.
8. The clock distribution circuit of claim 7 , wherein the state machine is configured to transition to a state based on at least its lead/lag input signal.