Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed
View Patent ↗A packet processor has a packet memory manager configured to store a page walk link list, receive a descriptor and initiate a page walk through the page walk link list in response to the descriptor and without a prompt from transmit direct memory access circuitry. The packet memory manager is configured to receive an indicator of a single page packet and read a new packet in response to the indicator without waiting to obtain page state associated with the page of the single page packet.
1. A packet processor, comprising:
a packet memory manager configured to
store a page walk link list;
receive a descriptor of a first packet;
initiate a page walk through the page walk link list in response to the descriptor of the first packet and without a prompt from transmit direct memory access circuitry;
receive an indicator that the first packet is a single page packet; and
read a second packet in response to the indicator without waiting to obtain page state associated with the first packet.
2. The packet processor of claim 1 wherein the indictor is a single bit.
3. The packet processor of claim 1 wherein the packet memory manager is further configured to
guarantee that the state of a first page of a packet is written by the time the descriptor of the packet is received;
apply a first latency to a second page of the packet, wherein the first latency is the difference between the latency of a packet processor ingress port to fill a full page with packet data and the maximum latency of a control block issuing a descriptor; and
apply a second latency to each additional page of the packet, wherein the second latency is the latency of the packet processor ingress port to fill a full page with packet data.
4. A packet processor, comprising:
a packet memory manager configured to
receive a single bit indicator that a first packet is a single page;
read a second packet in response to the single bit indicator without waiting to obtain page state associated with the first packet;
store a page walk link list;
receive a descriptor of the first packet; and
initiate a page walk through the page walk link list in response to the descriptor and without a prompt from transmit direct memory access circuitry.
5. A packet processor, comprising:
a packet memory manager configured to
receive a single bit indicator that a first packet is a single page; and
read a second packet in response to the single bit indicator without waiting to obtain page state associated with the first packet,
guarantee that the state of a first page of a packet is written by the time the descriptor of the packet is received;
apply a first latency to a second page of the packet, wherein the first latency is the difference between the latency of a packet processor ingress port to fill a full page with packet data and the maximum latency of a control block issuing a descriptor; and
apply a second latency to each additional page of the packet, wherein the second latency is the latency of the packet processor ingress port to fill a full page with packet data.