Voltage regulator with adaptive bias network
A low drop-out voltage regulator includes an error amplifier that generates an amplified error voltage, the error amplifier including a first input for receiving a reference voltage, a second input for receiving a feedback voltage, a bias terminal for receiving an adaptive bias current, and an output. A pass gate providing an output voltage includes a first input connected to a supply voltage and a second input connected to the error amplifier output. A feedback network generating the feedback voltage includes a first terminal connected to the output of the pass gate and a second terminal connected to the second input of the error amplifier. An adaptive bias network providing the adaptive bias current includes a first transistor connected to the bias terminal of the error amplifier, a second transistor connected to the first transistor as a current mirror, and a third transistor connected in parallel with the pass gate.
1. A low drop-out (LDO) voltage regulator comprising:
an error amplifier configured to generate an amplified error voltage, the error amplifier having a first input terminal for receiving a reference voltage, a second input terminal for receiving a feedback voltage, a current bias terminal for receiving an adaptive bias current, and an output terminal;
a pass gate configured to provide an output voltage to at least one external component, the pass gate having a first input terminal, a second input terminal and an output terminal, the first input terminal of the pass gate being connected to a supply voltage and the second input terminal being connected to the output terminal of the error amplifier;
a voltage feedback network configured to generate the feedback voltage, the voltage feedback network having a first terminal connected to the output terminal of the pass gate and a second terminal connected to the second input terminal of the error amplifier; and
an adaptive bias network configured to provide the adaptive bias current to the error amplifier, the adaptive bias network having a first transistor, a second transistor, and a third transistor, the first transistor connected to the current bias terminal of the error amplifier, the second transistor connected to the first transistor as a current mirror, and the third transistor having a first input terminal connected to the supply voltage and a second input terminal connected to the second input terminal of the pass gate.
2. The LDO voltage regulator of claim 1 , wherein the adaptive bias current through the first transistor is proportional to a current through the second transistor, a current through the third transistor is proportional to an output load current, and a current through the error amplifier scales proportionally with the output load current.
3. The LDO voltage regulator of claim 1 , further comprising an auxiliary bias network connected to the current bias terminal of the error amplifier to prevent bistable operation.
4. The LDO voltage regulator of claim 3 , wherein the auxiliary bias network comprises a resistor, a fourth transistor, and a fifth transistor, the resistor having a first terminal connected to the supply voltage and a second terminal connected to the fourth transistor, the fourth transistor connected to the fifth transistor as a current mirror, and the fifth transistor connected to the current bias terminal of the error amplifier.
5. The LDO voltage regulator of claim 1 , wherein the error amplifier includes a diode-connected transistor connected to the output terminal of the error amplifier that is configured to have a size selected to enhance bandwidth of the error amplifier.
6. The LDO voltage regulator of claim 1 , wherein the adaptive bias network includes a resistor-capacitor network configured to provide stability to the LDO voltage regulator.