System and method to provide non-coherent access to a coherent memory system
View Patent ↗In one embodiment, a system comprises a memory and a memory controller that provides a cache access path to the memory and a bypass-cache access path to the memory, receives requests to read graph data from the memory on the bypass-cache access path and receives requests to read non-graph data from the memory on the cache access path. A method comprises receiving a request at a memory controller to read graph data from a memory on a bypass-cache access path, receiving a request at the memory controller to read non-graph data from the memory through a cache access path, and arbitrating, in the memory controller, among the requests using arbitration.
1. A system comprising:
a memory;
a memory controller providing a cache access path to the memory and a bypass-cache access path to the memory, the memory controller receiving requests to read deterministic finite automata (DFA), non-deterministic finite automata (NFA), or hyper finite automata (HFA) graph data from the memory on the bypass-cache access path and receiving requests to read non-DFA, -NFA or -HFA graph data from the memory on the cache access path, the non-DFA, -NFA or -HFA graph data being packet data.
2. The system of claim 1 where the cache access path receives requests to read DFA, NFA, or HFA graph data and non-DFA, -NFA or -HFA graph data from the memory.
3. The system of claim 1 where the memory stores DFA, NFA, or HFA graph data and non-DFA, -NFA or -HFA graph data.
4. The system of claim 1 where the memory controller reads the requested DFA, NFA, or HFA graph data or non-DFA, -NFA or -HFA graph data.
5. The system of claim 1 where the memory controller receives the requests to read DFA, NFA, or HFA graph data from a co-processor.
6. The system of claim 5 where the co-processor includes at least one of a deterministic automata processing unit, a nondeterministic automata processing unit, and a hyper-finite automata processing unit.
7. The system of claim 5 where the co-processor is configured to stop sending read requests to the memory controller to stop the reading of selected DFA, NFA, or HFA graph data from the memory on the bypass-cache access path when the selected DFA, NFA, or HFA graph data is being written to the memory on the cache access path.
8. The system of claim 1 where the memory controller receives requests to read DFA, NFA, or HFA graph data and non-DFA, -NFA or -HFA graph data from a cache controller.
9. The system of claim 1 , where the memory controller receives requests to write data to memory on the cache access path.
10. The system of claim 1 , where the memory controller is configured to arbitrate among requests from the cache access path and the bypass-cache access path using at least one of fixed priority arbitration, round-robin arbitration, and weighted round-robin arbitration.
11. The system of claim 1 , wherein the DFA, NFA, or HFA graph data is non-sequentially addressed data and non-DFA, -NFA or -HFA graph data is serially addressed data.
12. A method comprising:
receiving one or more requests at a memory controller to read deterministic finite automata (DFA), non-deterministic finite automata (NFA), or hyper finite automata (HFA) graph data from a memory on a bypass-cache access path;
receiving one or more requests at the memory controller to read non-DFA, -NFA or -HFA graph data from the memory through a cache access path, the non-DFA, -NFA or -HFA graph data being packet data;
arbitrating, in the memory controller, among the requests using at least one of fixed priority arbitration, round-robin arbitration, and weighted round-robin arbitration.
13. The method of claim 12 further comprising receiving one or more requests at the memory controller to read non-DFA, -NFA or -HFA graph data and graph data from the memory through a cache access path.
14. The method of claim 12 further comprising reading from the memory the requested DFA, NFA, or HFA graph data or non-DFA, -NFA or -HFA graph data.
15. The method of claim 12 where the memory controller receives the requests to read DFA, NFA, or HFA graph data from a co-processor.
16. The method of claim 15 where the co-processor includes at least one of a deterministic automata processing unit, a nondeterministic automata processing unit, and a hyper-finite automata processing unit.
17. The method of claim 12 where the memory controller receives the requests to read non-DFA, -NFA or -HFA graph data and DFA, NFA, or HFA graph data from a cache controller through the cache access path.
18. The method of claim 12 further comprising receiving one or more requests to write data to memory on the cache access path.
19. The method of claim 12 further comprising stopping the reading of selected DFA, NFA, or HFA graph data from the memory on the bypass-cache access path while the selected DFA, NFA, or HFA graph data is being written to the memory on the cache access path.
20. The method of claim 12 where the memory stores DFA, NFA, or HFA graph data and non-DFA, -NFA or -HFA graph data.
21. The method of claim 12 , wherein the DFA, NFA, or HFA graph data is non-sequentially addressed data and non-DFA, -NFA or -HFA graph data is serially addressed data.