System and method to reduce memory access latencies using selective replication across multiple memory ports
View Patent ↗In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system further comprises a first address hashing unit configured to receive a request including at least one virtual memory address. Each virtual memory address is associated with a replication factor, and the virtual memory address refers to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address. The hardware based address refers to data in the memory ports within a subset indicated by the corresponding subset index.
1. A system comprising:
a plurality of memory ports, the plurality of memory ports distributed into a plurality of subsets, each subset identified by a subset index;
a first address hashing unit configured to receive a request including at least one virtual memory address, each virtual memory address associated with a replication factor, the virtual memory address referring to data, translate the replication factor into a corresponding subset index based on the virtual memory address, and convert the virtual memory address to a hardware based memory address, the hardware based address referring to data in at least one of the memory ports within a subset indicated by the corresponding subset index; and
a memory replication controller configured to direct requests to the hardware based address to the plurality of memory ports within the subset indicated by the corresponding subset index.
2. The system of claim 1 , further comprising a second address hashing unit configured to receive a request for data including at least one virtual memory address, and to convert each virtual memory address to a hardware based memory address, the hardware based memory address referring to a separate one of the plurality of memory ports.
3. The system of claim 2 , wherein the first address hashing unit is coupled to a plurality of inspection engines and a cache controller, wherein each inspection engine is configured to issue requests to the memory replication controller through the first address hashing unit and the second address hashing unit is coupled with the cache controller, wherein the cache controller is configured to issue requests to the plurality of memory ports through the second address hashing unit.
4. The system of claim 2 , wherein the first and second address hashing units are configured to modify the order that virtual memory address requests are distributed across the plurality of memory ports.
5. The system of claim 2 , wherein the plurality of memory ports is configured to store data in a hardware based memory address.
6. The system of claim 2 , wherein the second address hashing unit is configured to convert any given virtual memory address to a predetermined hardware based memory address.
7. The system of claim 1 , wherein the first address hashing unit is configured to convert any given virtual memory address to a predetermined hardware based memory address.
8. The system of claim 1 , wherein each of the hardware based addresses referring to a separate one of the plurality of memory ports within a subset has a same relative address within each of the plurality of memory ports.
9. The system of claim 1 , wherein the replication factor indicates a number of replications of a data structure in the plurality of memory ports.
10. The system of claim 1 , wherein a number of replications is an exponential power of two.
11. The system of claim 1 , wherein the replication factor of a given data is determined by a prediction of the frequency the given data will be read.
12. The system of claim 1 , wherein within a given graph, data nodes with the same replication factor are stored in the virtual memory in a group of addresses and the data nodes are assigned virtual memory addresses in at least one of ascending and descending order according to their replication factor.
13. The system of claim 1 , wherein a host or software has reserved sequential virtual memory addresses for each replication of a plurality of data.
14. The system of claim 1 , wherein the subset index includes at least one of bits of the virtual memory address and modified bits of the virtual memory address to access the data in the plurality of memory ports.
15. The system of claim 1 , wherein the memory replication controller is further configured to direct requests to the hardware based address to the plurality of memory ports within the subset indicated by the corresponding subset index based on at least one of an individual wait time and outstanding memory requests.
16. A method comprising:
distributing a plurality of memory ports into a plurality of subsets, each subset identified by a subset index;
receiving a request, at a first address hashing unit, with at least one virtual memory address and each virtual memory address associated with a replication factor, each virtual memory address referring to data;
translating, at the first address hashing unit, the replication factor into a corresponding subset index based on the virtual memory address;
converting, at the first address hashing unit, the virtual memory address to a hardware based memory address, the hardware based address referring to a separate one of the plurality of memory ports within a subset indicated by the corresponding subset index; and
directing requests, in a memory replication controller, to the hardware based address to the one of the plurality of memory ports.
17. The method of claim 16 , further comprising:
receiving, at a second address hashing unit, a request for data including at least one virtual memory address,
converting, at the second address hashing unit, each virtual memory address to a hardware based memory address, the hardware based memory address referring to a separate one of the plurality of memory ports.
18. The method of claim 17 , wherein the first address hashing unit is coupled with a plurality of inspection engines and a memory replication controller, wherein each inspection engine is configured to issue requests to the memory replication controller through the first address hashing unit, and the second hashing unit is coupled with a cache controller, wherein the cache controller is configured to issue read and requests to the plurality of memory controllers through the second address hashing unit.
19. The method of claim 17 , wherein the first and second address hashing units are configured to modify the order virtual memory address requests are distributed across the plurality of memory ports.
20. The method of claim 17 , wherein the plurality of memory ports is configured to store data in a hardware based memory address.
21. The method of claim 17 , wherein within a given graph, a data node with the same replication factor are stored in the virtual memory in a sequential group of addresses and the data nodes are assigned virtual memory addresses in at least one of ascending and descending order according to their replication factor.
22. The method of claim 17 , wherein the first and second address hashing units are configured to modify the order requests are distributed across the ports.
23. The method of claim 17 , wherein the second address hashing unit is configured to convert any given virtual memory address to the same hardware based memory address.
24. The method of claim 16 , wherein the first address hashing unit is configured to convert any given virtual memory address to the same hardware based memory address.
25. The method of claim 16 , wherein each of the hardware based addresses referring to a separate one of the plurality of memory ports within a subset has a same relative address within each of the plurality of memory ports.
26. The method of claim 16 , wherein the replication factor indicates a number of replications of a data structure in the plurality of memory ports.
27. The method of claim 16 , wherein the replication factor is an exponential power of two.
28. The method of claim 16 , wherein the replication factor of a given data is determined by a prediction of the frequency the given data will be read.
29. The method of claim 16 , wherein the subset index includes at least one of bits of the virtual memory address and modified bits of the virtual memory address to access the data in the plurality of memory ports.
30. The method of claim 16 , wherein the memory replication controller is further configured to direct requests to the hardware based address to the plurality of memory ports within the subset indicated by the corresponding subset index based on at least one of an individual wait time and outstanding memory requests.