IP Library Granted Patent US 7,205,785
Granted Patent B1
US 7,205,785 · App. 11/040,266 · Granted Apr 17, 2007

Apparatus and method for repairing logic blocks

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Quick Facts
Patent No.
US 7,205,785
App. No.
11/040,266
Granted
Apr 17, 2007
Kind
B1
Abstract

An apparatus is described comprising: a set of logic blocks configured to perform designated data processing functions; a set of redundant logic blocks also configured to perform the designated data processing functions; and a logic block selector module to replace one or more of the set of logic blocks with one or more of the set of redundant logic blocks according to specified logic block replacement conditions.

Claims (23)

1. An apparatus comprising:

a plurality of logic blocks on a cryptographic processor, each of the plurality of logic blocks performing specified cryptographic processing functions; and

a logic block selector to select a first subset of the plurality of logic blocks to be enabled based on test results from tests performed on each of the plurality of logic blocks, wherein said logic block selector comprises a plurality of binary storage elements for storing a binary code, the binary code indicating which of the plurality of logic blocks are included within the first subset.

2. The apparatus as in claim 1 wherein the binary storage elements comprise a plurality of fuses, the binary code being generated based on which of the plurality of fuses are blown.

3. The apparatus as in claim 1 wherein the binary storage elements comprise a non-volatile memory device.

4. An apparatus comprising:

a plurality of logic blocks on a cryptographic processor, each of the plurality of logic blocks performing specified cryptographic processing functions, wherein the logic blocks are cryptographic execution units to process data according to predefined cryptographic program code and further wherein the predefined cryptographic program code comprises cryptographic microcode specifying one or more primitive cryptographic operations; and

a logic block selector to select a first subset of the plurality of logic blocks to be enabled based on test results from tests performed on each of the plurality of logic blocks.

5. A method comprising:

fabricating a plurality of logic blocks on a cryptographic processor, each of the plurality of logic blocks performing specified cryptographic processing functions;

testing the logic blocks to determine which, if any, are damaged;

enabling only those logic blocks which are undamaged; and

disabling one or more of the undamaged logic blocks so that the total number of enabled logic blocks is equal to a predetermined number.

6. A method comprising:

fabricating a plurality of logic blocks on a cryptographic processor, each of the plurality of logic blocks performing specified cryptographic processing functions;

testing the logic blocks to determine which, if any, are damaged; and

enabling only those logic blocks which are undamaged, wherein a logic block selector to enable those logic blocks comprises a plurality of binary storage elements for storing a binary code, the binary code indicating which of the plurality of logic blocks are included within a first subset of the logic blocks to be enabled.

7. The method as in claim 6 wherein the binary storage elements comprise a plurality of fuses, the binary code being generated based on which of the plurality of fuses are blown.

8. The method as in claim 6 wherein the binary storage elements comprise a non-volatile memory device.

9. A method comprising:

fabricating a plurality of logic blocks on a cryptographic processor, each of the plurality of logic blocks performing specified cryptographic processing functions, wherein the logic blocks are cryptographic execution units to process data according to predefined cryptographic program code, and further wherein the cryptographic program code comprises cryptographic microcode specifying one or more primitive cryptographic operations;

testing the logic blocks to determine which, if any, are damaged; and

enabling only those logic blocks which are undamaged.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
CHANGE OF NAME Recorded Jan 11, 2019
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 049367/0717 →
RELEASE OF SECURITY INTEREST Recorded Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
SECURITY AGREEMENT Recorded Aug 17, 2016
From: CAVIUM, INC.; CAVIUM NETWORKS LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039715/0449 →
MERGER Recorded Jul 18, 2011
From: CAVIUM NETWORKS, INC.
To: CAVIUM, INC.
Reel/Frame 026610/0478 →