Clock gated delay line based on setting value
View Patent ↗In an embodiment, a delay circuit includes a delay line with a clock input signal and a delayed clock output signal that is based on a setting value. Each delay element of the delay line receives one of several delay element select signals and outputs a delayed signal based on the delay element select signal. The setting value may be a binary encoded value representing the desired delay. The delay element select signals may correspond to a thermometer encoded value of the binary encoded setting value.
1. A delay circuit comprising:
a delay line configured to receive a clock input signal, a setting value and a plurality of delay element select signals and to output a delayed clock signal based on the setting value,
the delay line comprising a plurality of delay elements connected in series, each delay element configured to receive one of the plurality of delay element select signals and output a delayed signal based on the delay element select signal,
wherein each delay element is a multiplexer having a first input configured to receive an input signal corresponding to the outputs of the delay element preceding in the series, a second input connected to ground and a multiplexer select input connected to the corresponding delay element select signal.
2. The delay circuit of claim 1 , wherein the setting value is a binary encoded value.
3. The delay circuit of claim 1 , wherein the delay element select signals correspond to a thermometer encoded value.
4. The delay circuit of claim 3 , wherein the delay element select signals correspond to a thermometer encoded representation of a binary encoded setting value.