Method and apparatus for supporting wide operations using atomic sequences
View Patent ↗Implementations of wide atomic sequences are achieved by augmenting a load operation designed to initiate an atomic sequence and augmenting a conditional storing operation that typically terminates the atomic sequence. The augmented load operation is designed to further allocate a memory buffer besides initiating the atomic sequence. The conditional storing operation is augmented to check the allocated memory buffer for any data stored therein. If one or more data words are detected in the memory buffer, the conditional storing operation stores the detected data word(s) and another word provided as operand in a concatenation of memory locations. The achieved wide atomic sequences enable the hardware system to support wide memory operations and wide operations in general.
1. A method comprising:
initiating, by a processor, an atomic sequence by executing an operation designed to initiate the atomic sequence and allocate a memory buffer;
storing one or more data words in a concatenation of one or more memory locations by executing a conditional storing operation, the conditional storing operation being designed to automatically check the memory buffer allocated for any data stored therein, and store the one or more data words based on a result of checking the memory buffer; wherein the operation designed to initiate the atomic sequence is a load operation designed to initiate the atomic sequence, and executing the load operation designed to initiate the atomic sequence includes loading a data word; and
storing data in the memory buffer allocated by executing one or more regular storing operations within the atomic sequence, wherein storing one or more data words by executing a conditional storing operation includes:
storing one or more first data words, associated with data stored in the memory buffer, and a second data word in a concatenation of two or more memory locations, the one or more first data words and the second data word having a cumulative width greater than a data word width associated with the processor.
2. The method as recited in claim 1 further comprising loading at least one data word by executing at least one regular load operation.
3. The method as recited in claim 1 , wherein the one or more first data words, associated with data stored in the memory buffer, represent one or more outputs of one or more first instances of a base operation and the second data word represents an output of a second instance of the base operation, the one or more first data words and the second data word, as stored in the concatenation of the two or more memory locations, represent an output of a wide operation corresponding to the base operation.
4. The method as recited in claim 3 further comprising executing the one or more first instances of the base operation and the second instance of the base operation within the atomic sequence.
5. The method as recited in claim 1 , wherein the operation designed to initiate the atomic sequence operates on a memory location residing within a single memory line.
6. The method as recited in claim 1 , wherein any regular load operation or regular storing operation executed within the atomic sequence operates on a memory location residing within a single memory line.
7. A method comprising:
initiating, by a processor, an atomic sequence by executing an operation designed to initiate the atomic sequence and allocate a memory buffer;
storing one or more data words in a concatenation of one or more memory locations by executing a conditional storing operation, the conditional storing operation being designed to automatically check the memory buffer allocated for any data stored therein, and store the one or more data words based on a result of checking the memory buffer, wherein the operation designed to initiate the atomic sequence has a memory register carrying a static value as destination; and
storing data in the memory buffer allocated by executing one or more regular storing operations within the atomic sequence, wherein storing one or more data words by executing a conditional storing operation includes:
storing one or more first data words, associated with data stored in the memory buffer, and a second data word in a concatenation of two or more memory locations, the one or more first data words and the second data word having a cumulative width greater than a data word width associated with the processor.
8. The method as recited in claim 7 , wherein the one or more first data words, associated with data stored in the memory buffer, represent one or more outputs of one or more first instances of a base operation and the second data word represents an output of a second instance of the base operation, the one or more data first words and the second data word as stored in the concatenation of the two or more memory locations represent an output of a wide operation corresponding to the base operation.
9. The method as recited in claim 8 further comprising executing the one or more first instances of the base operation and the second instance of the base operation prior to initiating the atomic sequence.
10. The method as recited in claim 7 , wherein the operation designed to initiate the atomic sequence operates on a memory location residing within a single memory line.
11. The method as recited in claim 7 , wherein any regular load operation or regular storing operation executed within the atomic sequence operates on a memory location residing within a single memory line.
12. A processor device comprising:
a core processor; and
a memory buffer associated with the core processor,
the core processor being configured to:
initiate an atomic sequence by executing an operation designed to initiate the atomic sequence and allocate a memory buffer;
store one or more data words in a concatenation of one or more memory locations by executing a conditional storing operation, the conditional storing operation being designed to automatically check the memory buffer allocated for any data stored therein, and store the one or more data words based on a result of checking the memory buffer, wherein the operation designed to initiate the atomic sequence is a load operation designed to initiate the atomic sequence, and in executing the load operation designed to initiate the atomic sequence, the core processor is further configured to load a data word; and
store data in the memory buffer allocated by executing one or more regular storing operations within the atomic sequence, wherein in storing the one or more data; words by executing a conditional storing operation, the core processor is further configured to store one or more first data words, associated with data stored in the memory buffer, and a second data word in a concatenation of two or more memory locations, the one or more first data words and the second data word having a cumulative width greater than a data word width associated with the processor.
13. The processor device as recited in claim 12 , wherein the core processor is further configured to load at least one data word by executing at least one regular load operation.
14. The processor device as recited in claim 12 , wherein the one or more first data words, associated with data stored in the memory buffer, represent one or more outputs of one or more first instances of a base operation and the second data word represents an output of a second instance of the base operation, the one or more first data words and the second data word, as stored in the concatenation of the two or more memory locations, represent an output of a wide operation corresponding to the base operation.
15. The processor device as recited in claim 14 , the core processor is further configured to execute the one or more first instances of the base operation and the second instance of the base operation within the atomic sequence.
16. The processor device as recited in claim 12 , wherein the operation designed to initiate the atomic sequence operates on a memory location residing within a single memory line.
17. The processor device as recited in claim 12 , wherein any regular load operation or regular storing operation executed within the atomic sequence operates on a memory location residing within a single memory line.
18. A processor device comprising:
a core processor; and
a memory buffer associated with the core processor,
the core processor being configured to:
initiate an atomic sequence by executing an operation designed to initiate the atomic sequence and allocate a memory buffer;
store one or more data words in a concatenation of one or more memory locations by executing a conditional storing operation, the conditional storing operation being designed to automatically check the memory buffer allocated for any data stored therein, and store the one or more data words based on a result of checking the memory buffer, wherein the operation designed to initiate the atomic sequence has a memory register carrying a static value as destination; and
store data in the memory buffer allocated by executing one or more regular storing operations within the atomic sequence, wherein in storing the one or more data words by executing a conditional storing operation, the core processor is further configured to store one or more first data words, associated with data stored in the memory buffer, and a second data word in a concatenation of two or more memory locations, the one or more first data words and the second data word having a cumulative width greater than a data word width associated with the processor.
19. The processor device as recited in claim 18 , wherein the one or more first data words, associated with data stored in the memory buffer, represent one or more outputs of one or more first instances of a base operation and the second data word represents an output of a second instance of the base operation, the one or more data first words and the second data word as stored in the concatenation of the two or more memory locations represent an output of a wide operation corresponding to the base operation.
20. The processor device as recited in claim 18 , wherein the core processor is further configured to execute the one or more first instances of the base operation and the second instance of the base operation prior to initiating the atomic sequence.
21. The processor device as recited in claim 18 , wherein the operation designed to initiate the atomic sequence operates on a memory location residing within a single memory line.
22. The processor device as recited in claim 18 , wherein any regular load operation or regular storing operation executed within the atomic sequence operates on a memory location residing within a single memory line.