Method and system for providing data integrity in storage systems
View Patent ↗A method and system for performing data integrity process is provided. The method includes selecting a cyclic redundancy code (“CRC”) mode from amongst append, validate and keep, and validate and remove mode. If the append mode is selected, then CRC is appended after each data block boundary. A CRC seed value is incremented for each data block providing a unique CRC value for each data block. If validate and keep mode is selected, then CRC accompanying any data is compared to CRC that may have been accumulated. If validate and remove mode is selected, then CRC is first validated and then CRC is removed before data is sent out. The system includes CRC logic that allows firmware running on an adapter to select one of plural CRC modes including append, validate and keep, and validate and remove mode.
1. A method for managing data integrity in an adapter, comprising:
receiving data in a receive and/or transmit path;
determining if a cyclic redundancy code (“CRC”) mode is enabled; and
selecting a CRC mode from among plural modes including append mode, validate and keep mode, and validate and remove mode; wherein if the append mode is selected, then CRC is appended after each data block boundary.
2. The method of claim 1 , wherein adapter firmware code may be used to select a particular mode based on certain register bits.
3. The method of claim 1 , wherein if the validate and keep mode is selected, then CRC accompanying any data is compared to accumulated CRC in real time while data is being sent to a host system and if an error occurs after the comparison, an interrupt is generated and data with CRC from a storage system are sent to the host system.
4. The method of claim 1 , wherein if the validate and remove mode is selected, then CRC is first validated and then CRC is removed before data is sent, without involving a host system or a storage system and any errors are reported to an adapter processor.
5. The method of claim 1 , wherein during an increment mode CRC seed value is incremented for each data block providing a unique CRC value for each data block.
6. The method of claim 5 , wherein an optional field and CRC are sent with a data block and the optional field is used to insert custom information.
7. A system for managing data integrity in receive and transmit path of an adapter, comprising:
a processor executing firmware code for selecting one of plural modes for implementing cyclic redundancy code (“CRC”) including append mode, validate and keep mode, and validate and remove mode, wherein during append mode, a CRC engine determines CRC for each data block and CRC seed value is incremented for each data block such that each data block has a unique CRC value.
8. The system of claim 7 , wherein register bits are used for enabling and disabling the plural modes for implementing CRC.
9. The system of claim 7 , wherein during the append mode each data block is associated with an optional field for inserting custom information.
10. The system of claim 7 , wherein during the validate and keep mode, a CRC engine compares CRC for data with accumulated CRC information in real time while data is being sent to a host system.
11. The system of claim 10 , wherein an interrupt is generated if an error occurs after the comparison and CRC received from a storage system in a receive path is sent to the host system.
12. The system of claim 7 , wherein during the validate and remove mode, CRC is validated and then CRC information is removed before data is sent without involving a host system or a storage system.
13. An adapter in a redundant array of independent disks (“RAID”) controller that is coupled to a host system and a storage media, comprising:
a processor executing firmware code for selecting one of plural modes for implementing cyclic redundancy code (“CRC”),wherein the plural CRC modes include append mode, validate and keep mode, and validate and remove mode and during the append mode, a CRC engine determines CRC for each data block and CRC seed value is incremented for each data block such that each data block has a unique CRC value.
14. The adapter of claim 13 , wherein register bits are used for enabling and disabling the plural modes for implementing CRC.
15. The adapter of claim 13 , wherein during the append mode each data block is associated with an optional field which is used for inserting custom information.
16. The adapter of claim 13 , wherein during the validate and keep mode, a CRC engine compares CRC for data with accumulated CRC information in real time while data is being sent to the host system.
17. The adapter of claim 16 , wherein an interrupt is generated if an error occurs after the comparison and CRC received from the storage system is sent to the host system.
18. The adapter of claim 13 , wherein during the validate and remove mode, CRC is validated and CRC information is removed before data is sent without involving the host system or the storage system.
19. The adapter of claim 13 , wherein the adapter is coupled to the host system via a PCI and/or PCI-X interface.