On-chip memory (OCM) physical bank parallelism
View Patent ↗According to an example embodiment, a processor is provided including an integrated on-chip memory device component. The on-chip memory device component includes a plurality of memory banks, and multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle.
1. An integrated on-chip memory device component, comprising:
a plurality of memory banks; and
multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, enabling access to multiple memory banks for multiple independent data access requests, wherein each data access request includes a memory address with a first set of bits indicative of a memory bank, among the plurality of memory banks, and a second set of bits indicative of a memory row within the memory bank indicated by the first set of bits, among the plurality of memory banks, per clock cycle, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per clock cycle.
2. An integrated on-chip memory device component as in claim 1 , wherein each memory bank, among the plurality of memory banks, is accessible by one or more of the multiple logical ports.
3. An integrated on-chip memory device component as in claim 1 , wherein each memory bank, among the plurality of memory banks, is accessible by each of the multiple logical ports.
4. An integrated on-chip memory device component as in claim 1 , wherein data of different types are assigned storage in different memory banks among the plurality of memory banks.
5. An integrated on-chip memory device component as in claim 4 , wherein assigning storage to data of different types in different memory banks, among the plurality of memory banks, is modifiable by a host processor.
6. An integrated on-chip memory device component as in claim 1 , wherein the data access request is of a type including a read type, a write type, or idle type.
7. An integrated on-chip memory device component as in claim 6 , wherein the data access request further includes a third set of bits indicative of the type of the data access request.
8. An integrated on-chip memory device component as in claim 7 , wherein the first set and the second set of bits is ignored if the data access request is of idle type.
9. An integrated on-chip memory device component as in claim 7 further comprising an input multiplexer configured to route each data access request to a corresponding single-ported memory bank.
10. An integrated on-chip memory device component as in claim 7 further comprising an output multiplexer configured to assign a memory bank, among the plurality of memory banks, to a respective logical output port.
11. An integrated on-chip memory device component as in claim 1 , wherein a memory bank, among the plurality of memory banks, has one or more read type only request ports.
12. An integrated on-chip memory device component as in claim 1 , wherein a memory bank, among the plurality of memory banks, has one or more write type only request ports.
13. An integrated on-chip memory device component as in claim 1 , wherein a memory bank, among the plurality of memory banks, has one or more ports, each port capable of servicing either a read type request or a write type request during a clock cycle.
14. An integrated on-chip memory device component as in claim 1 , wherein the plurality of memory banks are single-ported memory banks.
15. A method of accessing an integrated on-chip memory device component, the method comprising:
providing access to a plurality of memory banks of the integrated on-chip memory device component through multiple logical ports, each logical port coupled to one or more of the plurality of memory banks, each memory bank accessible by a single logical port per clock cycle and each logical port accessing a single memory bank per cycle, wherein providing access to the plurality of memory banks includes providing access for multiple independent data access requests, wherein each data access request includes a memory address with a first set of bits indicative of a memory bank, among the plurality of memory banks, and a second set of bits indicative of a memory row within the memory bank indicated by the first set of bits.
16. A method as in claim 15 , wherein the data access request, among the multiple data access requests, is of a type including a read type, a write type, or idle type.
17. A method as in claim 16 further comprising employing, in the data access request a third set of bits to indicate the type of the data access request.
18. A method as in claim 17 , wherein the first set and the second set of bits is ignored if the data access request is of idle type.
19. A method as in claim 15 , further comprising the step of assigning storage to data of different types in different memory banks, among the plurality of memory banks.
20. A method as in claim 19 , wherein assigning storage to data of different types in different memory banks, among the plurality of memory banks, is modifiable by a host processor.