Distributed interrupt scheme in a multi-processor system

1. A system, comprising:

a plurality of logic devices including a distributor and redistributors configured in a hierarchical tree structure to distribute one or more incoming interrupts to at least one of a plurality of last-level redistributors;

a plurality of processing elements, each of the processing elements having an associated interrupt bus address and including a CPU interface operatively coupled to the shared interrupt bus and a CPU core operatively coupled to the CPU interface;

a shared interrupt bus coupling the plurality of last-level redistributors and the plurality of the processing elements;

wherein each of the plurality of last-level redistributors is configured to:

transfer the one or more incoming interrupts over the shared interrupt bus based on the interrupt bus address according to a first clock domain to at least one of the plurality of the processing elements a CPU interface of which operates according to a second clock domain having a clock frequency that is different than that of the first clock domain; and

transfer data to and from the shared interrupt bus according to the clock frequency of the first clock domain, and each of the plurality of the processing elements is configured to transfer data to and from the shared interrupt bus via the processing element's CPU interface according to the clock frequency of the second clock domain.

2. The system of claim 1 , wherein the clock frequency of the first clock domain is lower than the clock frequency of the second clock domain.

3. The system of claim 1 , further comprising a bus buffer coupled to the shared interrupt bus to synchronize transfers over the shared interrupt bus between the first clock domain and the second clock domain.

4. The system of claim 1 , wherein the one or more incoming interrupts include interrupt messages defining at least a type of interrupt.

5. The system of claim 1 , wherein each of the plurality of last-level redistributors is configured to transfer one or more interrupt packets over the shared interrupt bus where each of the one or more interrupt packet includes an address field containing the interrupt bus address of a destination processing element and an interrupt message field containing an interrupt message.

6. The system of claim 1 , further comprising one or more bus arbitrators to arbitrate access to the shared interrupt bus among the plurality of processing elements and the plurality of last-level redistributors.

7. A method of distributing one or more interrupts in a system having a plurality of processing elements, each of the processing elements including a CPU interface operatively coupled to the shared interrupt bus and a CPU core operatively coupled to the CPU interface, comprising:

distributing one or more incoming interrupts through a plurality of logic devices including a distributor and redistributors configured in a hierarchical tree structure to at least one of a plurality of last-level redistributors;

transferring the one or more incoming interrupts by the at least one of a plurality of last-level redistributors over the shared interrupt bus based on the interrupt bus address according to a first clock domain to at least one of the plurality of the processing elements a CPU interface of which operates according to a second clock domain having a clock frequency that is different than that of the first clock domain; and

transferring data by each of the plurality of last-level redistributors to and from the shared interrupt bus according to the clock frequency of the first clock domain signal and transferring data by each of the plurality of the processing elements via the processing element's CPU interface to and from the shared interrupt bus according to the clock frequency of the second clock domain signal.

8. The method of claim 7 , wherein the clock frequency of the first clock domain signal is lower than the clock frequency of the second clock domain signal.

9. The method of claim 7 , further comprising:

buffering the shared interrupt bus to synchronize transfers over the shared interrupt bus between a first clock domain and a second clock domain.

10. The method of claim 7 , wherein the incoming interrupts include interrupt messages defining at least a type of interrupt.

11. The method of claim 7 , further comprising:

transferring, from the redistributors, interrupt packets over the shared interrupt bus, where each interrupt packet includes an address field containing the interrupt bus address of a destination processing element and an interrupt message field containing an interrupt message.

12. The method of claim 7 , further comprising:

arbitrating access to the shared interrupt bus among the processing elements and the plurality of last-level redistributors.

13. A system, comprising:

a plurality of means configured in a hierarchical tree structure to distribute one or more incoming interrupts to at least one of a plurality of last level means;

a plurality of processing elements, each of the processing elements having an associated bus address and including a CPU interface operatively coupled to the shared interrupt bus and a CPU core operatively coupled to the CPU interface; and

a shared interrupt bus coupling the of a plurality of last-level means and the processing elements;

wherein each of the plurality of last level means is configured to:

transfer the one or more incoming interrupts over the shared interrupt bus based on the interrupt bus address according to a first clock domain to at least one of the plurality of the processing elements a CPU interface of which operates according to a second clock domain having a clock frequency that is different than that of the first clock domain; and

transfer data to and from the shared interrupt bus according to the clock frequency of the first clock domain and each of the plurality of the processing elements is configured to transfer data to and from the shared interrupt bus via the processing element's CPU interface according to the clock frequency of the second clock domain.

14. A non-transitory computer-readable memory comprising:

executable instructions that when executed by at least one processor of an electronic design automation system (or integrated circuit fabrication system), that when executed cause the at least one processor to:

provide a plurality of logic devices including a distributor and redistributors configured in a hierarchical tree structure to distribute one or more incoming interrupts to at least one of a plurality of last-level redistributors,

provide a plurality of processing elements, each of the processing elements having an associated interrupt bus address and including a CPU interface operatively coupled to the shared interrupt bus and a CPU core operatively coupled to the CPU interface:

provide a shared interrupt bus coupling the plurality of last-level redistributors and the plurality of the processing elements;

wherein each of the plurality of last-level redistributors is configured to:

transfer the one or more of the incoming interrupts over the shared interrupt bus based on the interrupt bus address according to a first clock domain to at least one of the plurality of the processing elements a CPU interface of which operates according to a second clock domain having a clock frequency that is different than that of the first clock domain; and

transfer data to and from the shared interrupt bus according to the clock frequency of the first clock domain and each of the plurality of the processing elements is configured to transfer data to and from the shared interrupt bus via the processing element's CPU interface according to the clock frequency of the second clock domain.