Granted Patent B1

US 9,256,562 · App. 13/644,535 · Granted Feb 9, 2016

Abstract

Claims (38)

1. A machine implemented method, comprising:

a processor for a computing device allocating an address range with a physical address to write to an intermediate storage location at a device communicating with the computing device;

the processor assigning a plurality of identifiers to a plurality of storage locations at the device other than the intermediate storage location, where each of the plurality of storage locations is assigned one of the plurality of identifiers and the address range of the intermediate storage location is smaller than an address range for the plurality of storage locations;

the processor configuring the device communicating with the computing device for writing information at the intermediate storage location of the device and at the plurality of storage locations;

the computing device sending the address for the intermediate storage location with a write value;

an interface of the device decoding the write value to write the data that needs to be written at one of the plurality of storage locations a first identifier identifying the one of the plurality of storage locations; and

the device first writing the data at the intermediate storage location and then updating the one of the plurality of storage locations identified by the first identifier.

2. The method of claim 1 , wherein the processor receives a virtual address corresponding to the intermediate storage location, translates the virtual address to the physical address of the intermediate storage location and provides the physical address to a device interface.

3. The method of claim 2 , wherein the device interface uses the physical address to generate a message for the device to write to the intermediate storage location.

4. The method of claim 3 , wherein the device interface is a PCI-Express interface.

5. The method of claim 1 , wherein the intermediate storage location is an intermediate register that is addressable using a PCI-Express address.

6. The method of claim 1 , wherein the plurality of storage locations are a plurality of writable registers used for storing instructions from the processor of the computing device.

7. The method of claim 1 , wherein the device is a network adapter.

8. The method of claim 1 , wherein the device is a host bus adapter.

9. The method of claim 1 , wherein the device is a converged network adapter.

10. A system, comprising:

a processor for a computing device communicating with a device via an interconnect, where the device includes an intermediate storage location and a plurality of storage locations for storing data received from the processor;

wherein the processor assigns a plurality of identifiers to a plurality of storage locations, each of the plurality of storage locations being assigned one of the plurality of identifiers;

wherein the processor allocates an address range with a physical address to write to the intermediate storage location; configures the device for writing information to any of the plurality of storage locations by using the intermediate storage location; and sends the physical address for the intermediate storage location with a write value;

wherein the address range of the intermediate storage location is smaller than an address range for the plurality of storage locations;

wherein an interface for the device decodes the write value to write data that needs to be written at one of the plurality of storage locations with a first identifier identifying the one of the plurality of storage locations; and

wherein the device first writes the data at the intermediate storage location and then updates the one of the plurality of storage locations identified by the first identifier.

11. The system of claim 10 , wherein the processor receives a virtual address corresponding to the intermediate storage location, translates the virtual address to the physical address of the intermediate storage location and provides the address to a device interface.

12. The system of claim 11 , wherein the device interface uses the physical address to generate a message for the device to write to the intermediate storage location.

13. The system of claim 12 , wherein the device interface is a PCI-Express interface.

14. The system of claim 10 , wherein the intermediate storage location is an intermediate register that is addressable using a PCI-Express address.

15. The system of claim 10 , wherein the plurality of storage locations are a plurality of writable registers used for storing instructions from the processor of the computing device.

16. The system of claim 10 , wherein the device includes a network adapter, a host bus adapter and a converged network adapter.

17. A device, comprising:

an intermediate storage location and a plurality of storage locations for storing data from a processor for a computing device communicating with the device via an interconnect;

wherein the processor assigns a plurality of identifiers to the plurality of storage locations, each of the plurality of storage locations being assigned one of the plurality of identifiers;

wherein the processor allocates an address range with a physical address to write to the intermediate storage location; configures the device for writing information to any of the plurality of storage locations by using the intermediate storage location; and sends, from the computing device, the address for the intermediate storage location with a write value;

wherein the address range of the intermediate storage location is smaller than an address range for the plurality of storage locations;

wherein the device decodes the write value to write data that needs to be written at one of the plurality of storage locations with a first identifier identifying the one of the plurality of storage locations; and

wherein the device first writes the data at the intermediate storage location and then updates the one of the plurality of storage locations identified by the first identifier.

18. The device of claim 17 , wherein the processor receives a virtual address corresponding to the intermediate storage location, translates the virtual address to the physical address of the intermediate storage location and provides the address to a device interface.

19. The device of claim 17 , wherein the intermediate storage location is an intermediate register that is addressable using a PCI-Express address.

20. The device of claim 17 , wherein the device includes a network adapter, a host bus adapter and a converged network adapter.

Assignments (7)