Resistively loaded single stage differential amplifier having zero volt common mode input
View Patent ↗A resistively folded single stage differential amplifier capable of accommodating a low input common mode without impacting the performance of a bias current source, while also providing a high input impedance to allow for the use of the linear termination resistors. The differential amplifier provides an amplified output signal with a common mode referenced to an upper bound of an input power supply. The differential amplifier includes an input sub-stage and a transistor sub-stage resistively folding the input sub-stage.
1. A differential amplifier comprising:
an input sub-stage configured to accommodate a zero volt common mode input and provide a high input impedance; and
a transistor sub-stage configured to resistively fold the input sub-stage forming a single stage using a resistive load, the resistive load configured to provide an output signal with a common mode referenced to an upper bound of an input power supply, the output signal having a non-inverting output and an inverting output.
2. The differential amplifier of claim 1 wherein the input sub-stage further comprises:
a pair of input transistors; and
a third transistor configured to supply a bias current.
3. The differential amplifier of claim 2 wherein the pair of input transistors and the third transistor are p-channel MOS transistors.
4. The differential amplifier of claim 3 wherein the pair of input transistors are configured to accommodate the zero volt common mode input without impacting the performance of the third transistor.
5. The differential amplifier of claim 1 wherein the transistor sub-stage further comprises a plurality of n-channel MOS transistors configured to supply a second biasing current source.
6. The differential amplifier of claim 1 wherein at least two transistors of the transistor sub-stage resistively fold the input sub-stage to output nodes, in a manner allowing the input to have a direct effect on the output signal.
7. A method of amplification comprising:
receiving a zero volt common mode input signal while providing an amplifier high input impedance; and
outputting an amplified output signal, with a common mode referenced to an upper bound of an input power supply, via a transistor sub-stage resistively folding an input sub-stage using a resistive load, the output signal having a non-inverting output and an inverting output.
8. The method of claim 7 wherein the input sub-stage further comprises a pair of input transistors and a third transistor supplying a bias current.
9. The method of claim 8 wherein the pair of input transistors and the third transistor are p-channel MOS transistors.
10. The method of claim 9 wherein receiving the zero volt common mode input signal is performed by the pair of input transistors without impacting the performance of the third transistor.
11. The method of claim 7 wherein transistor sub-stage further comprises a plurality of n-channel MOS transistors supplying a second bias current.
12. The method of claim 7 wherein resistively folding further comprises:
supplying a bias current to the transistor sub-stage with use of the input sub-stage; and
directly affecting the output signal via the bias current.
13. A differential amplifier comprising:
an input sub-stage comprising;
an input pair of p-channel transistors configured to accommodate a zero volt common mode input and provide a high input impedance; and
a third transistor configured to supply a bias current;
a transistor sub-stage resistively folding the input sub-stage forming a single stage using a resistive load, the transistor sub-stage further comprising:
a first set of n-channel MOS transistors configured to receive the bias current through the resistive load; and
a second set of n-channel MOS transistors configured to supply a second bias current, where the first and second set of n-channel MOS transistors are further configured to provide an output signal with a common mode referenced to an upper bound of an input power supply and the output signal directly affected by the input and having a non-inverting output and an inverting output.
14. A differential amplifier comprising:
means for accommodating a zero volt common mode input and providing a high input impedance; and
means for resistively folding using a resistive load configured to provide an output signal with a common mode referenced to an upper bound of an input power supply, the output signal having a non-inverting output and an inverting output.
15. The differential amplifier of claim 1 wherein the resistive load comprises two resistors.
16. The method of claim 7 wherein the resistive load comprises two resistors.