Packet parsing engine

1. An engine comprising:

a DMEM configured to store packet data for multiple packets, wherein the DMEM is divided into a plurality of DMEM subsections;

a plurality of register sets configured to store parsing instructions and/or parse results, wherein each register set of the plurality of register sets is paired with a DMEM subsection of the plurality of DMEM subsections;

an arithmetic logic unit (ALU) configured to perform packet parsing operations,

wherein, the engine is configured to:

parse a first packet stored in a first DMEM section after a first register set is initialized for the first packet, wherein the first register set and the first DMEM section are paired;

during parsing the first packet, load a second packet in a second DMEM subsection and initialize a second register set for the second packet, wherein the second register set and the second DMEM section are paired; and

parse the second packet after the parsing the first packet completes.

2. The engine of claim 1 , wherein the engine is comprised in a cluster of engines comprising a plurality of engines, and wherein the plurality of engines are configured to access a shared memory, and wherein the engine is configured to receive data from the shared memory or to send data to the shared memory.

3. The packet parsing engine of claim 2 , wherein each of the plurality of engines is configured to execute a parsing instruction with an added delay from a previous engine executing the parsing instruction.

4. The engine of claim 1 , wherein the engine is further configured to, during parsing the second packet, unloading the first packet.

5. The engine of claim 1 , wherein the engine is further configured to swap among pairs of DEM subsection and register set based on an address bit to addresses of the plurality of DEM sections.

6. The engine of claim 1 , wherein the parsing instructions are 64 bits wide, and wherein the DMEM, the plurality of register sets, and the arithmetic logic unit communicate via 16 bit data.

7. A method of parsing packet data by a packet parsing engine, wherein the engine includes a DMEM, a plurality of register sets, and an arithmetic units (ALU), the method comprising:

storing a first packet in a first DMEM subsection, wherein the DMEM is configured to store multiple packets, wherein the DMEM is divided into a plurality of DMEM subsections,

initializing a first register set for the first packet, wherein the plurality of register sets are configured to store parsing instructions and/or parse results, wherein each register set of the plurality of register sets is paired with a DMEM subsection of the plurality of DMEM subsections, and wherein further the first DMEM subsection and the first register set are paired;

parsing the first packet by using the ALU;

during parsing the first packet, loading a second packet in a second DMEM subsection and initializing a second register set for the second packet, wherein the second register set and the second DMEM section are paired; and

parsing the second packet after the parsing the first packet completes.

8. The method of claim 7 , wherein the engine is one engine of a plurality of engines, the method further comprising accessing a shared memory that is configured to be accessed by the plurality of engines, wherein the accessing includes receiving data from the shared memory or sending data to the shared memory.

9. The method of claim 8 further comprising each of the plurality of engines decoding and executing the parsing instruction with a delay from a previous engine executing the parsing instruction.

10. The method of claim 7 , wherein the parsing instructions are wide 64 bits.

11. The method of claim 7 , further comprising sending communications among the DMEMs, the plurality of register sets, and the arithmetic logic unit via 16 bit data.

12. A packet parser comprising:

a cluster of engines, wherein each engine of the cluster of engines comprises:

a DMEM configured to store packet data for multiple packets, wherein the DMEM is divided into a plurality of DMEM subsections,

a plurality of register sets configured to store parsing instructions and/or parse results, wherein each register set of the plurality of register sets is paired with a DMEM subsection of the plurality of DMEM subsections;

an arithmetic logic unit (ALU) configured to perform packet parsing operations,

wherein, the engine is configured to:

parse a first packet stored in a first DMEM section after a first register set is initialized for the first packet, wherein the first register set and the first DMEM section are paired;

during parsing the first packet, load a second packet in a second DMEM subsection and initialize a second register set for the second packet, wherein the second register set and the second DMEM section are paired; and

parse the second packet after the parsing the first packet completes;

a shared memory accessible to the cluster of engines; and

an arbiter coupled to the cluster of engines and the shared memory and configured to arbitrate access to the shared memory among the cluster of engines.

13. The packet parser of claim 12 , wherein the engine is further configured to, during parsing the second packet, unloading the first packet.

14. The packet parser of claim 12 , wherein the engine is further configured to swap among pairs of DEM subsection and register set based on an address bit to addresses of the plurality of DEM sections.

15. The packet parser of claim 12 , wherein the arbiter is configured to delay a response to an engine request for accessing the shared memory.

16. The packet parser of claim 15 , wherein the arbiter is further configured to cause the cluster of engines to have different execution time for parsing packets.