IP Library Assignment 047202/0690
Patent Assignment
Reel/Frame 047202/0690

Conversion

Recorded: 2018-10-06 Pages: 9
Assignor
CAVIUM, INC.
Executed: 2018-09-21
Assignee
CAVIUM, LLC
2315 N. FIRST STREET, SAN JOSE, CALIFORNIA, 95131
Covered Properties (45)
System and Method for Low-Latency Multimedia Streaming
Patent: 9,781,477 →
Application: 12/774,608 →
Publication: US 2011/0276710
Method and System for Skipping Over Group(S) of Rules Based on Skip Group Rule
Patent: 9,275,336 →
Application: 14/145,374 →
Publication: US 2015/0186781
Multi-Rule Approach to Encoding a Group of Rules
Patent: 9,544,402 →
Application: 14/145,918 →
Publication: US 2015/0189046
Processing Request Keys Based on a Key Size Supported by Underlying Processing Elements
Patent: 9,268,855 →
Application: 14/150,550 →
Publication: US 2015/0195262
Method and Apparatus for Compiling Search Trees for Processing Request Keys Based on a Key Size Supported by Underlying Processing Elements
Patent: 9,432,284 →
Application: 14/150,572 →
Publication: US 2015/0195194
Methods and Systems for Single Instruction Multiple Data Programmable Packet Parsers
Application: 14/150,602 →
Publication: US 2015/0195383
Packet Parsing Engine
Application: 14/150,622 →
Publication: US 2015/0195384
Condition Code Approach for Comparing Rule and Packet Data That Are Provided in Portions
Patent: 9,667,446 →
Application: 14/150,761 →
Publication: US 2015/0193689
Block Mask Register Key Processing by Compiling Data Structures to Traverse Rules and Creating a New Rule Set
Patent: 9,647,947 →
Application: 14/152,817 →
Publication: US 2015/0201047
Method and an Apparatus for Work Packet Queuing, Scheduling, and Ordering with Conflict Queuing
Application: 14/170,955 →
Publication: US 2015/0220872
Method and Apparatus for Performing a Weighted Queue Scheduling Using a Set of Fairness Factors
Application: 14/542,298 →
Publication: US 2016/0142333
Packet Scheduling Using Hierarchical Scheduling Process
Application: 14/542,350 →
Publication: US 2016/0142341
Packet Scheduling Using Hierarchical Scheduling Process with Priority Propagation
Application: 14/542,393 →
Publication: US 2016/0142331
Automated Flip-Flop Insertions in Physical Design Without Perturbation of Routing
Patent: 9,600,614 →
Application: 14/634,446 →
Publication: US 2016/0224709
Repeater Insertions Providing Reduced Routing Perturbation Caused by Flip-Flop Insertions
Patent: 9,600,620 →
Application: 14/664,680 →
Publication: US 2016/0275230
Method and Apparatus for Bypass Routing of Multicast Data Packets and Avoiding Replication to Reduce Overall Switch Latency
Application: 14/671,900 →
Publication: US 2016/0285744
Identifying Inversion Error in Logic Equivalence Check
Patent: 9,547,733 →
Application: 14/675,307 →
Publication: US 2016/0292329
Approach for Chip-Level Flop Insertion and Verification Based on Logic Interface Definition
Application: 14/675,342 →
Publication: US 2016/0291932
Determination of Flip-Flop Count in Physical Design
Patent: 9,792,400 →
Application: 14/675,356 →
Publication: US 2017/0068769
Approach for Logic Signal Grouping and Rtl Generation Using Xml
Application: 14/675,403 →
Publication: US 2016/0292330
Method and Apparatus for Using Multiple Linked Memory Lists
Application: 14/675,450 →
Publication: US 2016/0294735
Carry Chain for Simd Operations
Application: 14/940,538 →
Publication: US 2016/0139920
Implementing 128-Bit Simd Operations on a 64-Bit Datapath
Application: 14/940,585 →
Publication: US 2016/0140079
Method and System for Compressing Data for a Translation Look Aside Buffer (Tlb)
Patent: 9,703,722 →
Application: 14/940,679 →
Publication: US 2016/0140050
Approach for Interfacing a Pipeline with Two or More Interfaces in a Processor
Application: 14/940,982 →
Publication: US 2016/0140059
Distributing Resource Requests in a Computing System
Patent: 9,678,717 →
Application: 14/941,082 →
Publication: US 2016/0139883
Sharing Resources in a Multi-Context Computing System
Application: 14/941,182 →
Publication: US 2016/0139950
Method and System for Compressing Data for a Translation Look Aside Buffer (Tlb)
Patent: 9,772,952 →
Application: 15/598,719 →
Publication: US 2017/0255566
Flowlet Scheduler for Multicore Network Processors
Application: 15/608,852 →
Publication: US 2018/0351692
Issuing Instructions Based on Resource Conflict Constraints in Microporcessor
Application: 15/875,611 →
Publication: US 2019/0227805
Timestamp-Based Packet Switching Using a Trie Data Structure
Application: 15/894,732 →
Publication: US 2018/0359195
External Dqs Bi-Directional Loopback with Use of Feed Forward Equalization Path
Application: 15/934,804 →
Publication: US 2019/0293709
Write and Read Common Leveling for 4-Bit Wide Drams
Application: 16/039,922 →
Write and Read Common Leveling for 4-Bit Wide Drams
Application: 16/040,249 →
Voq-Based Network Switch Architecture Using Multi-Stage Arbitration Fabric Scheduler
Application: 16/054,627 →
Publication: US 2020/0044985
Compressing Like Magnitude Partial Products in Multiply Accumulation
Application: 16/115,117 →
Publication: US 2020/0073637
Methods and Systems for Distributing Memory Requests
Application: 16/128,369 →
Method and System for Compressing Data for a Translation Look Aside Buffer (Tlb)
Application: 62/079,706 →
Carry Chain for Simd Operations
Application: 62/079,762 →
Implementing 128-Bit Simd Operations on a 64-Bit Datapath
Application: 62/079,881 →
Multiple Memory Management Units
Application: 62/079,893 →
Distributing Resource Requests in a Computing System
Application: 62/079,933 →
Sharing Resources in a Multi-Context Computing System
Application: 62/079,941 →
Novel Approach for Report Generation and of a Preliminary Flop Assertion in a Multi-Block System and Further Identification of Correct Flop Insertion That Does Not Exceed Preliminary Design Constraints
Application: 62/112,054 →
Timestamp-Based Packet Switching Using a Trie Data Structure
Application: 62/516,577 →
Related Assignments (24)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jul 25, 2012
From: MIGHANI, FARHAD; DUENAS, ALBERTO; NGUYEN, NGUYEN; GARCIA, GORKA
To: CAVIUM, INC.
Reel/Frame 028635/0826 →
Assignment of Assignor's Interest Jan 8, 2014
From: SNYDER, WILSON PARKHURST, II; KATZ, DANIEL ADAM
To: CAVIUM INC.
Reel/Frame 031922/0153 →
Assignment of Assignor's Interest Jan 8, 2014
From: SNYDER, WILSON PARKHURST, II; KATZ, DANIEL ADAM; OGALE, VARADA RAMESH
To: CAVIUM INC.
Reel/Frame 031922/0232 →
Assignment of Assignor's Interest Jan 31, 2014
From: WORRELL, FRANK
To: CAVIUM, INC.
Reel/Frame 032103/0908 →
Assignment of Assignor's Interest Feb 3, 2014
From: SNYDER, WILSON PARKHURST, II; KESSLER, RICHARD EUGENE; DEVER, DANIEL EDWARD; KRAVITZ, DAVID
To: CAVIUM, INC.
Reel/Frame 032118/0880 →
Assignment of Assignor's Interest Feb 26, 2014
From: WORRELL, FRANK; GOYAL, RAJAN; BILLA, SATYANARAYANA LAKSHMIPATHI
To: CAVIUM, INC.
Reel/Frame 032299/0250 →
Assignment of Assignor's Interest May 13, 2014
From: GOYAL, RAJAN; BULLIS, KENNETH
To: CAVIUM, INC.
Reel/Frame 032877/0893 →
Assignment of Assignor's Interest May 13, 2014
From: GOYAL, RAJAN; BULLIS, KENNETH
To: CAVIUM, INC.
Reel/Frame 032877/0189 →
Assignment of Assignor's Interest May 13, 2014
From: GOYAL, RAJAN; BULLIS, KENNETH A.
To: CAVIUM, INC.
Reel/Frame 032877/0344 →
Assignment of Assignor's Interest May 13, 2014
From: GOYAL, RAJAN; BULLIS, KENNETH
To: CAVIUM, INC.
Reel/Frame 032877/0582 →
Assignment of Assignor's Interest Dec 3, 2014
From: PANCHAGNULA, VAMSI; CHUNG, HEELOO
To: XPLIANT
Reel/Frame 034362/0599 →
Assignment of Assignor's Interest Dec 15, 2014
From: DANIEL, TSAHI; PANCHAGNULA, VAMSI
To: XPLIANT
Reel/Frame 034510/0718 →
Assignment of Assignor's Interest Dec 15, 2014
From: PANCHAGNULA, VAMSI; DANIEL, TSAHI; HAN, KEQIN
To: XPLIANT
Reel/Frame 034510/0456 →
Assignment of Assignor's Interest Apr 3, 2015
From: PANCHAGNULA, VAMSI; PATEL, SAURIN; HAN, KEQIN
To: XPLIANT
Reel/Frame 035329/0495 →
Assignment of Assignor's Interest Apr 3, 2015
From: JAYAKUMAR, NIKHIL; WANG, WEIHUANG; MA, WEINAN; AHLUWALIA, DAMAN
To: XPLIANT
Reel/Frame 035329/0629 →
Assignment of Assignor's Interest Apr 3, 2015
From: AHLUWALIA, DAMAN; JAYAKUMAR, NIKHIL
To: XPLIANT
Reel/Frame 035329/0411 →
Assignment of Assignor's Interest Apr 23, 2015
From: SINGH, CHIRINJEEV
To: XPLIANT
Reel/Frame 035483/0684 →
Assignment of Assignor's Interest Jun 10, 2015
From: WANG, WEIHUANG; THEIVENDRAN, PREMSHANTH; JAYAKUMAR, NIKHIL; SCHMIDT, GERALD
To: XPLIANT
Reel/Frame 035886/0038 →
Merger Aug 14, 2015
From: XPLIANT, INC.
To: CAVIUM NETWORKS LLC
Reel/Frame 036327/0190 →
Assignment of Assignor's Interest Nov 9, 2015
From: CAVIUM NETWORKS LLC
To: CAVIUM, INC.
Reel/Frame 036991/0534 →
Security Agreement Aug 17, 2016
From: CAVIUM, INC.; CAVIUM NETWORKS LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039715/0449 →
Release of Security Interest Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
Assignment of Assignor's Interest Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
Assignment of Assignor's Interest May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →