Write and read common leveling for 4-bit wide DRAMs

1. A method comprising:

at a memory controller, generating a first strobe signal associated with data signals of a first set of bits of a byte;

at the memory controller, generating a second strobe signal associated with data signals of a second set of bits of said byte;

obtaining a write leveling setting for said first strobe signal based on feedback of said first set of bits; and

while anchoring at said write leveling setting, adjusting a first delay line for said second strobe signal to obtain a first deskew setting based on feedback of said second set of bits.

2. The method of claim 1 , wherein said obtaining said write leveling setting comprises adjusting write leveling logic that is configured for delaying both said first strobe signal and said second strobe signal at said write leveling setting in write operations.

3. The method of claim 2 further comprising:

determining second deskew settings for second delay lines associated with said first set of bits; and

determining third deskew settings for third delay lines associated with said second set of bits.

4. The method of claim 3 , wherein said adjusting said write leveling logic comprises adjusting a delay component in said write leveling logic until any bit of said first set of bits asserts without regard to feedback of said second set of bits.

5. The method of claim 4 , wherein said adjusting said first delay line comprises:

responsive to said write leveling setting causing any bit of said second set of bits to assert, decreasing a setting of said first delay line until none of said second set of bits assert; and

incrementing said setting of said first delay line until any of said second set of bits asserts to obtain said first deskew setting.

6. The method of claim 5 , wherein said adjusting said first delay line comprises, responsive to said write leveling setting causing none of said second set of bits to assert, incrementing said setting of said first delay line setting until any of said second set of bits asserts to obtain said first deskew setting.

7. The method of claim 3 further comprising using said write leveling setting, said first deskew setting, said second deskew settings and said third deskew settings in memory write operations with a first data interface configuration of said memory controller.

8. The method of claim 7 further comprising:

with a second data interface configuration of said memory controller, determining a fourth deskew setting for said first delay line; and

using said fourth deskew setting to deskew a data bus inversion (DBI) signal in memory write operations with said second data interface configuration.

9. The method of claim 1 further comprising: adjusting a fifth delay line for said first strobe signal after said adjusting said write leveling logic and before obtaining said first deskew setting and, wherein said fifth delay lines has a higher adjustment resolution than said write leveling logic, wherein said adjusting said fifth delay line comprises: reviewing an assertion of any bit of said first set of bits; and decrementing a setting of said fifth delay line until none of said first set of bits assert.

10. A integrated circuit comprising:

memory control logic configured to generate a first strobe signal associated with a first set of bits of a byte and a second strobe signal associated with a second set of bits of said byte;

a first delay line for said second strobe signal;

second delay lines for said first set of bits;

third delay lines for said second set of bits;

a transmitting interface configured to transmit said first strobe signal and said second strobe signal to one or more memory storage devices;

write leveling logic comprising an adjustable delay component configured to delay both said first strobe signal and said second strobe signal, wherein said write leveling logic is configured to adjust said adjustable delay component to obtain a write leveling setting based on feedback of said first set of bits from one of said one or more memory storage devices; and

deskew control logic configured to, while said write leveling logic is anchored at said write leveling setting, adjust said first delay line to obtain a first deskew setting thereof based on feedback of said second set of bits from one of said one or more memory storage devices.

11. The integrated circuit of claim 10 , wherein said deskew control logic is further configured to:

determine second deskew settings for second delay lines associated with said first set of bits; and

determine third deskew settings for third delay lines associated with said second set of bits.

12. The integrated circuit of claim 10 , wherein said write leveling logic is configured to adjust said adjustable delay component until any bit of said first set of bits asserts to obtain said write leveling setting, wherein said adjustable delay component is adjusted without regard to feedback of said second set of bits.

13. The integrated circuit of claim 12 , wherein said deskew control logic is configured to adjust said first delay line by performing:

responsive to said write leveling setting causing any bit of said second set of bits to assert, decreasing a setting of said first delay line until none of said second set of bits assert; and

incrementing said setting of said first delay line setting until any of said second set of bits asserts to obtain said first deskew setting.

14. The integrated circuit of claim 12 , wherein said deskew control logic is configured to adjusting said first delay line by, responsive to said write leveling setting causing none of said second set of bits to assert, incrementing said setting of said first delay line until any of said second set of bits asserts to obtain said first deskew setting.

15. The integrated circuit of claim 11 , wherein said deskew control logic is further configured to use said write leveling setting, said first deskew setting, said second deskew settings and said third deskew settings in memory write operations with a first data interface configuration of said memory controller.

16. The integrated circuit of claim 15 , wherein said memory control logic is further configured to:

determine a fourth deskew setting for said first delay line; and

use said fourth deskew setting to deskew a data bus inversion (DBI) signal associated with both said first set and said second set of bits in memory write operations with a second data interface configuration of said memory controller.

17. The integrated circuit of claim 10 , wherein said first set of bits correspond to least-significant 4 bits of said byte, and wherein said second set of bits correspond to most-significant 4 bits of said byte.

18. A method of write deskew training, the method comprising:

at a memory controller, transmitting a first strobe signal and a second strobe signal respectively associated with a first set of bits of a byte and a second set of bits of the byte;

adjusting write leveling logic to obtain a write leveling setting based on feedback of said first set of bits and without regard to feedback of said second set of bits, wherein said write leveling logic is operable to delay both said first strobe signal and said second strobe signal at said write leveling setting during memory write operations;

with said write leveling logic anchored at said write leveling setting, adjusting a first delay line for said second strobe signal to obtain a first deskew setting based on feedback of said second set of bits;

determining second deskew settings for second delay lines associated with said first set of bits; and

determining third deskew settings for third delay lines associated with said second set of bits.

19. The method of claim 18 , wherein said adjusting said first delay line comprises:

when said write leveling setting causes any bit of said second set of bits to assert, decreasing a setting of said first delay line until none of said second set of bits assert; and

incrementing said setting of said first delay line until any of said second set of bits asserts to obtain said first deskew setting.

20. The method of claim 19 , wherein said adjusting said first delay line comprises, if said write leveling setting causes none of said second set of bits to assert, incrementing said setting of said first delay line setting until any of said second set of bits asserts to obtain said first deskew setting.

21. The method of claim 18 further comprising, before said first deskew setting is obtained and after said adjusting said write leveling logic, adjusting a fourth delay line for said first strobe signal, wherein said fourth delay line has a higher adjustment resolution than said write leveling logic, and wherein further said adjusting said fourth delay line comprises:

reviewing an assertion of any bit of said first set of bits; and

decrementing a setting of said fourth delay line until none of said first set of bits assert.