Method and system for compressing data for a translation look aside buffer (TLB)
An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.
1. A method of memory management, the method comprising:
storing compressed virtual address related data in a translation look aside buffer (TLB); and
accessing physical memory using the compressed virtual address related data.
2. The method of claim 1 further comprising mapping the compressed virtual address related data to a physical address.
3. The method of claim 1 further comprising:
receiving the virtual address related data at a content addressable memory (CAM); and
compressing the virtual address related data based on a location the data is stored within the CAM.
4. The method of claim 3 wherein the virtual address related data received by the CAM has a first bit length and the compressed virtual address related data has a second bit length which is smaller than the first bit length.
5. The method of claim 1 wherein the virtual address related data is at least one of: a Virtual Machine Identifier (VMID) and Address Space Identifier (ASID), the VMID and ASID being parsed from a context associated with a virtual address.
6. The method of claim 5 wherein the context is a logical data structure used by the TLB to identify a page table entry, the page table entry mapping a virtual address associated with the identifier to the physical address.
7. The method of claim 5 wherein receiving the virtual address related data includes parsing the VMID into a first CAM and parsing the ASID into a second CAM, wherein each CAM is configured to compress received data based on a location the data is stored in each respective CAM.
8. The method of claim 3 wherein compressing includes adjusting an allocation count in an allocation count register, the allocation count register being communicatively coupled to the CAM.
9. The method of claim 8 further comprising:
identifying a replacement virtual address related data in the CAM; and
decreasing a first allocation count in the allocation count register corresponding to the replacement data in the CAM.
10. The method of claim 9 further comprising:
if the virtual address related data is already represented in the CAM, increasing a second allocation count in the allocation count register corresponding to the virtual address related data stored in the CAM;
if the virtual address related data is not represented in the CAM, storing the identifier in a free location in the CAM and increasing a second allocation count in the allocation count register corresponding to the virtual address related data stored in free location in the CAM.
11. A system for memory management, the system comprising:
a translation look aside buffer (TLB) configured to store compressed virtual address related data; and
a memory management unit (MMU) configured to access physical memory using the compressed virtual address related data.
12. The system of claim 11 wherein the TLB is further configured to map the compressed virtual address related data to a physical address.
13. The system of claim 11 further comprising:
a content addressable memory (CAM) configured to receive the virtual address related data, the CAM further configured to compress the virtual address related data based on a location within the CAM the identifier is stored.
14. The system of claim 13 wherein the virtual address related data received by the CAM has a first bit length and the compressed virtual address related data has a second bit length which is smaller than the first bit length.
15. The system of claim 13 further comprising an allocation count register configured to store an allocation count, the allocation count register being communicatively coupled to the CAM.
16. The system of claim 15 wherein the MMU is further configured to:
identify a replacement virtual address related data in the CAM; and
decrease a first allocation count in the allocation count register corresponding to the replacement data in the CAM.
17. The system of claim 16 wherein the MMU is further configured to:
if the virtual address related data is already represented in the CAM, increase a second allocation count in the allocation count register corresponding to the virtual address related data stored in the CAM;
if the virtual address related data is not represented in the CAM, store the identifier in a free location in the CAM and increase a second allocation count in the allocation count register corresponding to the virtual address related data stored in free location in the CAM.
18. The system of claim 11 wherein the virtual address related data is at least one of: a Virtual Machine Identifier (VMID) and Address Space Identifier (ASID), the VMID and ASID being parsed from a context associated with a virtual address.
19. The system of claim 18 wherein the context is a logical data structure used by the TLB to identify a page table entry, the page table entry mapping a virtual address associated with the identifier to the physical address.
20. The system of claim 18 wherein the MMU is further configured to parse the VMID into a first CAM and parse the ASID into a second CAM, wherein each CAM is configured to compress received data based on a location the data is stored in each respective CAM.