Methods and systems for distributing memory requests

1. A computer-implemented method, comprising:

accessing a memory request comprising an address, wherein the memory request comprises a first operation associated with an instance of data;

selecting a group of caches from a plurality of groups of caches using a bit in the address;

selecting a cache in the group of caches using a first hash of the address; and

when the first operation results in a cache miss, performing a second operation to access a memory outside the cache, and otherwise processing the memory request at the cache according to the first operation.

2. The method of claim 1 , wherein said selecting a group of caches further comprises hashing the bit with selected other bits in the address.

3. The method of claim 2 , wherein the bit and the selected other bits are selected based on a specified distribution of a number of times each group of caches of the plurality of groups of caches is selected.

4. The method of claim 1 , wherein the first hash is configured based on a specified distribution of a number of times each cache in the group of caches is selected.

5. The method of claim 1 , further comprising, after said selecting a cache, selecting a set of cache lines from a plurality of sets of cache lines in the cache using a second hash of the address.

6. The method of claim 5 , wherein the second hash is configured based on a specified distribution of a number of times each set of cache lines of the plurality of sets of cache lines is selected.

7. The method of claim 5 , wherein which bits are hashed for said selecting a group of caches, which bits are selected for the first hash, and which bits are selected for the second hash, are independently programmable.

8. The method of claim 5 , wherein the second hash generates a set address corresponding to the set of cache lines that is selected, the method further comprising deriving the address of the memory request using a reverse hash of the set address.

9. The method of claim 5 , wherein the second operation comprises selecting a memory controller from a plurality of memory controllers using a third hash of the address, the memory controllers configured to enable access to the memory outside the cache.

10. The method of claim 9 , wherein the third hash is configured based on a specified distribution of a number of times each memory controller of the plurality of memory controllers is selected.

11. The method of claim 9 , wherein the second operation further comprises selecting a bank group and a bank from a plurality of bank groups and a respective plurality of banks in the memory using a fourth hash of the address.

12. The method of claim 11 , wherein the fourth hash is configured to achieve a specified distribution of a number of times each bank group of the plurality of bank groups and each bank of the respective plurality of banks is selected.

13. A system, comprising:

a processor; and

a plurality of caches coupled to the processor;

wherein the processor is operable for executing instructions that, when executed, perform operations comprising:

accessing a memory request comprising an address, wherein the memory request comprises a first operation associated with an instance of data;

using a bit in the address to select a group of caches from the plurality of caches;

performing a first hash of the address to select a cache in the group of caches;

unless the first operation results in a cache miss in the cache, processing the memory request at the cache according to the first operation; and

when the first operation results in a cache miss, performing a second operation to access memory coupled to the system.

14. The system of claim 13 , wherein said using a bit comprises hashing the bit with selected other bits in the address to select the group of caches.

15. The system of claim 13 , wherein the operations further comprise, after the cache is selected, performing a second hash of the address to select a set of cache lines from a plurality of sets of cache lines in the cache.

16. The system of claim 15 , further comprising a plurality of memory controllers coupled to the processor and configured to enable access to the memory, wherein the second operation comprises performing a third hash of the address to select a memory controller from the plurality of memory controllers.

17. The system of claim 16 , wherein the second operation further comprises performing a fourth hash of the address to select a bank group and a bank from a plurality of bank groups and a respective plurality of banks in the memory.

18. A system, comprising:

means for accessing a memory request comprising an address, wherein the memory request comprises a first operation associated with an instance of data;

means for selecting a group of caches from a plurality of groups of caches using a bit in the address;

means for performing a first hash of the address to select a cache in the group of caches;

means for performing a second operation to access a memory outside the cache when the first operation results in a cache miss; and

means for processing the memory request at the cache according to the first operation.

19. The system of claim 18 , further comprising means for hashing the bit with selected other bits in the address to select the group of caches.

20. The system of claim 18 , further comprising means for performing a second hash of the address to select a set of cache lines from a plurality of sets of cache lines in the cache.

21. The system of claim 20 , wherein the means for performing a second operation comprises means for performing a third hash of the address to select a memory controller from a plurality of memory controllers configured to enable access to the memory.

22. The system of claim 21 , further comprising means for performing a fourth hash of the address to select a bank group and a bank from a plurality of bank groups and a respective plurality of banks in the memory.