IP Library Granted Patent US 10,824,783
Granted Patent B2
US 10,824,783 · App. 14/675,403 · Granted Nov 3, 2020

Approach for logic signal grouping and RTL generation using XML

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Quick Facts
Patent No.
US 10,824,783
App. No.
14/675,403
Granted
Nov 3, 2020
Kind
B2
Abstract

Systems and methods for generating an RTL description based on logical signal groupings are described. Logical interfaces are declared in a compressed form, and logical signal grouping is defined in a markup document. The definitions from the markup document are used by expansion scripts to populate RTL modules and encapsulate block connectivity and functionality. Multiple interfaces can be created instantly, and interface definitions for common interfaces may be easily re-defined. Default values may be assigned to module outputs for testing purposes, allowing for multi-module simulations where certain modules are shelled-out.

Claims (45)

1. A method, performed by a processor, for generating a register transfer level (RTL) description using logical signal grouping, the method comprising:

generating a plurality of logical interface definitions, wherein the plurality of logical interface definitions define signals from an output module to an input module and comprise an interface rule;

defining a data structure in a structured document, wherein the data structure comprises a first set of logical interfaces, and wherein the structured document is used to define the logical signal grouping for each logical interface of the first set of logical interfaces;

executing an expansion script to generate a first RTL description using the structured document, wherein the first RTL description comprises a plurality of RTL modules that communicate using the plurality of logical interface definitions, wherein the first RTL description is populated based on the plurality of logical interface definitions, the interface rule, the logical signal grouping defined in the structured document, and the data structure, and wherein the generated first RTL description facilitates reuse of physical components of an integrated circuit (IC) without implementing physical changes to the physical components to accommodate different placements, routings, and orientations;

modifying a first logical interface from the first set of logical interfaces of the data structure to automatically generate a second RTL description based on the expansion script using the data structure defined in the structured document;

assigning a default value to a first output of a first RTL module of the plurality of RTL modules and testing a second RTL module of the plurality of RTL modules using the first output, wherein the assigning the default value comprises assigning a default value to a logical interface, related to the first RTL module, in the structured document; and

generating objects and sequence items based on the logical signal grouping, wherein the generated objects and the generated sequence items are to be used for error testing and use of drivers and monitors.

2. The method of claim 1 , wherein the first set of logical interfaces are bi-directional.

3. The method of claim 1 , further comprising assigning a default value to a control signal of the first set of logical interfaces.

4. The method of claim 1 , further comprising automatically generating a documentation file comprising a direction, a size, and a description of the signals.

5. The method of claim 1 , wherein the structured document is an XML, file.

6. The method of claim 1 , wherein the first RTL description comprises structured HDL code.

7. The method of claim 1 , wherein the first RTL description comprises an automatically generated struct comprising a plurality of signals.

8. The method of claim 1 , further comprising automatically generating an assertion based on the structured document for testing a condition of the first RTL module of the plurality of RTL modules.

9. A computer program product tangibly embodied in a computer-readable storage device and comprising instructions, that when executed by a processor, perform a method for generating a register transfer level (RTL) description using logical signal grouping, the method comprising:

generating a plurality of logical interface definitions, wherein the plurality of logical interface definitions define signals from an output module to an input module and comprise an interface rule;

defining a data structure in a structured document, wherein the data structure comprises a first set of logical interfaces, and wherein the structured document is used to define the logical signal grouping for each logical interface of the first set of logical interfaces;

executing an expansion script to generate a first RTL description using the structured document, wherein the first RTL description comprises a plurality of RTL modules that communicate using the plurality of logical interface definitions, wherein the first RTL description is populated based on the plurality of logical interface definitions, the interface rule, the logical signal grouping defined in the structured document, and the data structure, and wherein the generated first RTL description facilitates reuse of physical components of an integrated circuit (IC) without implementing physical changes to the physical components to accommodate different placements, routings, and orientations;

modifying a first logical interface from the first set of logical interfaces of the data structure to automatically generate a second RTL description based on the expansion script using the data structure defined in the structured document;

assigning a default value to a first output of a first RTL module of the plurality of RTL modules and testing a second RTL module of the plurality of RTL modules using the first output, wherein the assigning the default value comprises assigning a default value to a logical interface, related to the first RTL module, in the structured document; and

generating objects and sequence items based on the logical signal grouping, wherein the generated objects and the generated sequence items are to be used for error testing and use of drivers and monitors.

10. The method of claim 9 , wherein the first set of logical interfaces are bi-directional.

11. The method of claim 9 , further comprising assigning a default value to a control signal of the first set of logical interfaces.

12. The method of claim 9 , further comprising automatically generating a documentation file comprising a direction, a size, and a description of the signals.

13. The method of claim 9 , wherein the structured document is an XML file.

14. The method of claim 9 , wherein the first RTL description comprises structured HDL code.

15. The method of claim 9 , wherein the first RTL description comprises an automatically generated struct comprising a plurality of signals.

16. The method of claim 9 , further comprising automatically generating an assertion based on the structured document for testing a condition of the first RTL module of the plurality of RTL modules.

17. A system comprising:

at least one processor; and

at least one computer-readable storage device comprising instructions, that when executed by the at least one processor, cause performance of a method for generating a register transfer level (RTL) description using logical signal grouping, the method comprising:

generating a plurality of logical interface definitions, wherein the plurality of logical interface definitions define signals from an output module to an input module and comprise an interface rule;

defining a data structure in a structured document, wherein the data structure comprises a first set of logical interfaces, and wherein the structured document is used to define the logical signal grouping for each logical interface of the first set of logical interfaces;

executing an expansion script to generate a first RTL description using the structured document, wherein the first RTL description comprises a plurality of RTL modules that communicate using the plurality of logical interface definitions, wherein the first RTL description is populated based on the plurality of logical interface definitions, the interface rule, the logical signal grouping defined in the structured document, and the data structure, and wherein the generated first RTL description facilitates reuse of physical components of an integrated circuit (IC) without implementing physical changes to the physical components to accommodate different placements, routings, and orientations;

modifying a first logical interface from the first set of logical interfaces of the data structure to automatically generate a second RTL description based on the expansion script using the data structure defined in the structured document;

assigning a default value to a first output of a first RTL module of the plurality of RTL modules and testing a second RTL module of the plurality of RTL modules using the first output, wherein the assigning the default value comprises assigning a default value to a logical interface, related to the first RTL module, in the structured document; and

generating objects and sequence items based on the logical signal grouping, wherein the generated objects and the generated sequence items are to be used for error testing and use of drivers and monitors.

18. The method of claim 17 , wherein the first set of logical interfaces are bi-directional.

19. The method of claim 17 , further comprising assigning a default value to a control signal of the first set of logical interfaces.

20. The method of claim 17 , further comprising automatically generating a documentation file comprising a direction, a size, and a description of the signals.

21. The method of claim 17 , further comprising automatically generating an assertion based on the structured document for testing a condition of the first RTL module of the plurality of RTL modules.

22. The method of claim 17 , wherein the structured document is an XML file.

23. The method of claim 17 , wherein the first RTL description comprises structured HDL code.

24. The method of claim 17 , wherein the first RTL description comprises an automatically generated struct comprising a plurality of signals.

25. The method of claim 1 , further comprising, in response to changing a first logical interface definition of the plurality of logical interface definitions, wherein the first logical interface definition is in multiple RTL modules of the plurality of RTL modules: automatically changing, as a group, each instance of the first logical interface definition in each RTL module of the multiple RTL modules.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
CONVERSION Recorded Oct 6, 2018
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 047202/0690 →
RELEASE OF SECURITY INTEREST Recorded Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBER 14657403 NUMBER SHOULD BE 14675403 PREVIOUSLY RECORDED AT REEL: 039715 FRAME: 0449. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 21, 2016
From: CAVIUM, INC.; CAVIUM NETWORKS LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 041141/0872 →
SECURITY AGREEMENT Recorded Aug 17, 2016
From: CAVIUM, INC.; CAVIUM NETWORKS LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039715/0449 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: CAVIUM NETWORKS LLC
To: CAVIUM, INC.
Reel/Frame 036991/0534 →
MERGER Recorded Aug 14, 2015
From: XPLIANT, INC.
To: CAVIUM NETWORKS LLC
Reel/Frame 036327/0190 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2015
From: THEIVENDRAN, PREMSHANTH; WANG, WEIHUANG; HUTCHISON, GUY; SCHMIDT, GERALD
To: XPLIANT
Reel/Frame 035841/0955 →