The present disclosure relates to an add and decode hardware logic circuit for adding two n bit inputs, A and B. A series of n logic stages are each configured to perform a first operation of propagating a result of a preceding stage on the condition that the sum of A[m] and B[m] is equal to 0, wherein 0<=m<n, perform a second operation of performing a bitwise left shift by 2 m of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 1, or perform a third operation of performing a bitwise left shift by 2 m+1 of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 2. An output at the last stage provides a decoded sum of the inputs A and B.
1. A combined adder and decoder circuit, comprising:
n bit inputs, A and B, wherein n is greater than 1;
a hardware logic circuit with n logic stages, each logic stage having one or more gates, configured to:
perform a first operation of propagating a result of a preceding stage on the condition that the sum of A[m] and B[m] is equal to 0, wherein 0<=m<n;
perform a second operation of performing a bitwise left shift by 2 m of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 1;
perform a third operation of performing a bitwise left shift by 2 (m+1) of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 2;
an output at stage n providing a decoded sum of inputs A and B.
2. The circuit of claim 1 , wherein the output at stage n is 2 (n+1) bits wide.
3. The circuit of claim 1 , wherein the output at stage m is 2 (m+1) bits wide.
4. The circuit of claim 1 , wherein the operands A and B are each three-bits wide.
5. The circuit of claim 1 , wherein the decoded sum of the output at stage n and a constant C is obtained by performing a bitwise left shift on the output at stage n by C.
6. The circuit of claim 5 , wherein the constant C is 2.
7. The circuit of claim 5 , wherein the constant C is 3.
8. A method for combined adding and decoding in a hardware logic circuit, the method comprising:
receiving n bit inputs, A and B, wherein n is greater than 1;
for each logic stage having one or more gates, of n logic stages in the hardware logic circuit:
performing a first operation of propagating a result of a preceding stage on the condition that the sum of A[m] and B[m] is equal to 0, wherein 0<=m<n;
performing a second operation of performing a bitwise left shift by 2 m of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 1;
performing a third operation of performing a bitwise left shift by 2 (m+1) of the result of the preceding stage on the condition that the sum of A[m] and B[m] is equal to 2;
providing an output at stage n which is a decoded sum of inputs A and B.
9. The method of claim 8 , the method further providing a 2 (n+1) bits wide output at stage n.
10. The method of claim 8 , the method further providing a 2 (m+1) bits wide output at stage m.
11. The method of claim 8 , wherein the operands A and B are each three-bits wide.
12. The method of claim 8 , further comprising:
obtaining the decoded sum of the output at stage n and a constant C by performing a bitwise left shift on the output at stage n by C.
13. The method of claim 12 , wherein the constant C is 2.
14. The method of claim 12 , wherein the constant C is 3.