Apparatus and method for processing alternately configured longest prefix match tables
View Patent ↗A network switch includes a memory configurable to store alternate table representations of an individual trie in a hierarchy of tries. A prefix table processor accesses in parallel, using an input network address, the alternate table representations of the individual trie and searches for a longest prefix match in each alternate table representation to obtain local prefix matches. The longest prefix match from the local prefix matches is selected. The longest prefix match has an associated next hop index base address and offset value. A next hop index processor accesses a next hop index table in the memory utilizing the next hop index base address and offset value to obtain a next hop table pointer. A next hop processor accesses a next hop table in the memory using the next hop table pointer to obtain a destination network address.
1. A network switch, comprising:
a memory configurable to store alternate table representations of an individual trie in a hierarchy of tries, wherein the alternate table representations are optimized for different longest prefix match search strategies and memory optimization strategies;
a hardware prefix table processor to
access in parallel, using an input network address, the alternate table representations of the individual trie and search for a longest prefix match in each alternate table representation to obtain local prefix matches,
select the longest prefix match from the local prefix matches, wherein the longest prefix match has an associated next hop index base address and offset value;
a next hop index processor to access a next hop index table in the memory utilizing the next hop index base address and offset value to obtain a next hop table pointer; and
a next bop processor to access a next hop table in the memory using the next hop table pointer to obtain a destination network address.
2. The network switch of claim 1 wherein the alternate table representations include a sparse mode representation that identifies selected trie nodes.
3. The network switch of claim 2 wherein the sparse mode representation includes a branch identification and a stride value.
4. The network switch of claim 1 wherein the alternate table representations include a bit map mode representation with a bit map that identifies selected trie nodes.
5. The network switch of claim 4 wherein the bit map mode representation includes a branch identification and a stride value.
6. The network switch of claim l wherein the alternate table representations include a leaf-push representation that identifies selected trie nodes at the bottom of a trie.
7. The network switch of claim 6 wherein the leaf-push representation includes branch identification and a stride value.
8. The network switch of claim 1 wherein the prefix table processor is a hardware resource with a deterministic look-up latency.
9. The network switch of claim 1 wherein the alternate table representations include tables with different packet types in the same table.
10. The network switch of claim 9 wherein the different packet types includes IPV4 packets and IPV6 packets.
11. The network switch of claim 1 wherein the prefix table processor identifies a longest prefix match for a remote host and an exact match for a directly attached host.
12. The network switch of claim 11 wherein the prefix table processor identifies the longest prefix match for the remote host and the exact match for the directly attached host in the same table.
13. The network switch of claim 1 wherein the next hop index processor processes a block of next hop table entries to facilitate equal-cost multi-path routing.
14. The network switch of claim 13 wherein the block specifies up to 1024 paths.