Partitioned error code computation
View Patent ↗A circuit provides parallel computation of error codes for simultaneously received words. The words received simultaneously may be portions of a common data message, or may be portions of distinct data messages. Accordingly, the circuit selectively accumulates the error codes based on their association with successive data words, outputting an accumulated error code when the last word of a data message has been received and the respective error code is calculated. Based on such information, the error codes calculated in parallel can be output independently, accumulated with one another, or accumulated with the error codes of a previous or subsequent calculation cycle. Thus, the circuit dynamically provides a single parallel error code generation of a given width or multiple parallel error code generations, each of a width divisible by the given width.
1. A circuit for calculating an error code of a data message, comprising:
a first computation unit configured to receive a first word and generate a corresponding first error code;
a second computation unit configured to receive a second word and generate a corresponding second error code; and
a control circuit configured to 1) selectively accumulate the first and second error codes based on at least one control signal to provide an accumulated error code, 2) selectively loop back the accumulated error code to an input of the control circuit for further accumulation with a subsequent error code generated by at least one of the first and second computation units to provide a final accumulated error code based on the at least one control signal, and 3) selectively output at least one of the first error code, the second error code and the final accumulated error code based on the at least one control signal.
2. The circuit of claim 1 , wherein the at least one control signal indicates whether either of the first word and the second word is a final word of a data message.
3. The circuit of claim 2 , wherein the control circuit is further configured to accumulate the first and second error codes in response to the at least one control signal indicating that neither of the first and second words is a final word of data message.
4. The circuit of claim 2 , wherein the control circuit is further configured to accumulate a plurality of error codes generated by the first and second computation units in the absence of the control signal indicating that either of the first word and the second word is the final word of the data message, the plurality of error codes including the first and second error codes.
5. The circuit of claim 4 , wherein the plurality of error codes includes a third error code generated by one of the first and second computation units based on a third word.
6. The circuit of claim 1 , wherein the accumulated error code includes an accumulation of a third error code and at least one of the first and second error codes, the third error code being generated by one of the first and second computation units based on a third word.
7. The circuit of claim 1 , wherein the control circuit is further configured to accumulate at least one of the first and second error codes with at least a third error code, the third error code being generated by one of the first and second computation units in one of a previous or a subsequent calculation cycle.
8. The circuit of claim 1 , wherein the first and second words are portions of a data message.
9. The circuit of claim 1 , wherein the first word is a portion of a first data message and the second word is a portion of a second data message.
10. The circuit of claim 1 , wherein the first and second computation units each include a tree of interconnected exclusive-or (XOR) gates.
11. A method of calculating an error code of a data message comprising:
calculating a first error code from a first word;
calculating a second error code from a second word;
selectively accumulating the first and second error codes based on at least one control signal to provide an accumulated error code;
selectively looping back the accumulated error code for further accumulation with a subsequent error code generated by at least one of the first and second computation units to provide a final accumulated error code; and
selectively outputting at least one of the first error code, the second error code and the final accumulated error code based on the at least one control signal.
12. The method of claim 11 , wherein the at least one control signal indicates whether either of the first word and the second word is a final word of a data message.
13. The method of claim 12 , further comprising accumulating the first and second error codes in response to the at least one control signal indicating that neither of the first and second words is a final word of data message.
14. The method of claim 12 , further comprising accumulating a plurality of error codes generated by the first and second computation units in the absence of the control signal indicating that either of the first word and the second word is the final word of the data message, the plurality of error codes including the first and second error codes.
15. The method of claim 14 , wherein the plurality of error codes includes a third error code generated based on a third word.
16. The method of claim 11 , wherein the accumulated error code includes an accumulation of a third error code and at least one of the first and second error codes, the third error code being generated based on a third word.
17. The method of claim 11 , further comprising accumulating at least one of the first and second error codes with at least a third error code, the third error code being generated by one of the first and second computation units in one of a previous or a subsequent calculation cycle.
18. The method of claim 11 , wherein the first and second words are portions of a data message.
19. The method of claim 11 , wherein the first word is a portion of a first data message and the second word is a portion of a second data message.
20. The method of claim 11 , wherein calculating the first and second error codes includes applying the first and second words in parallel to respective trees of interconnected exclusive-or (XOR) gates.
21. A circuit for calculating an error code of a data message, comprising:
a first computation unit configured to generate first error codes corresponding to words in a first data stream;
a second computation unit configured to generate second error codes corresponding to words in a second data stream; and
a control circuit configured to 1) selectively accumulate the first and second error codes based on at least one control signal to generate accumulated error codes, 2) selectively loop back the accumulated error codes to an input of the control circuit for further accumulation with a subsequent error code generated by at least one of the first and second computation units to provide a final accumulated error code based on the at least one control signal, and 3) selectively output the first error codes, the second error codes and the final accumulated error codes based on the at least one control signal.
22. The circuit of claim 21 , wherein the at least one control signal indicates whether the words in the first and second data streams include a final word of a data message.