IP Library Granted Patent US 7,260,217
Granted Patent B1
US 7,260,217 · App. 10/092,328 · Granted Aug 21, 2007

Speculative execution for data ciphering operations

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Quick Facts
Patent No.
US 7,260,217
App. No.
10/092,328
Granted
Aug 21, 2007
Kind
B1
Abstract

In one embodiment, a computer-implemented method comprises receiving a data cipher operation. The method also comprises processing the data cipher operation. The processing of the operation includes generating a number of portions of ciphertext from plaintext, wherein a load operation associated with the generating of at least one portion of the ciphertext executes prior to a store operation associated with the generating of a prior portion of the ciphertext.

Claims (52)

1. A computer-implemented method executing in a processor, the method comprising:

receiving a request to perform for data ciphering of plaintext; and

processing the request based on a data structure stored in a memory coupled to the processor, wherein the processing comprises,

performing a first access of data from the data structure;

swapping the data from the first access;

data ciphering a first portion of the plaintext based on the swapped data from the first access;

performing a second access of data from the data structure prior to the swapping of the data from the first access;

performing the following, upon determining that the data from the first access does not equal the data from the second access,

swapping the data from the second access; and

data ciphering a second portion of the plaintext based on the swapped data from the second access in an iteration including data ciphering a first portion of the plaintext based on the swapped data from the first access; and

performing the following, upon determining that the data from the first access equals data from the second access,

reexecuting the performing of the second access of data from the data structure in an iteration that is subsequent to determining that the data from the first access does not equal the data from the second access;

swapping the data from the second access; and

data ciphering the second portion of the plaintext based on the swapped data from the second access.

2. The computer-implemented method of claim 1 , wherein the data ciphering comprises an RC4 operation.

3. The computer-implemented method of claim 1 , wherein the data structure comprises a substitution-box.

4. A co-processor coupled to a host processor and a host memory, the co-processor comprising:

an interface unit to retrieve a data encryption operation, a substitution (S)-box and plaintext associated with the data encryption operation from the host memory based on an instruction from the host processor; and

an execution unit coupled to the interface unit, the execution unit comprising,

a memory to store the plaintext and the S-box associated with the operation for the data cipher;

a microcontroller unit to schedule the data cipher operation; and

a RC4 unit to receive the data cipher operation, wherein the RC4 unit is to swap data stored in the S-box for data ciphering of a first portion of the plaintext wherein the RC4 unit is to read data stored in the S-box for data ciphering of a second portion of the plaintext, prior to completion of the swapping of data stored in the S-box for data ciphering of the first portion of the plaintext, and wherein the RC4 unit is to data cipher the second portion of the plaintext upon determining that the data being swapped in the S-box does not equal the data being read from the S-box.

5. The co-processor of claim 4 , wherein the RC4 unit is to data cipher the first portion of the plaintext.

6. The co-processor of claim 4 , wherein the RC4 unit is to swap data retrieved from the S-box for the data ciphering of the second portion of the plaintext upon determining that the data being swapped for the data ciphering of the first portion of the plaintext does not equal the data read from the S-box for data ciphering of the second portion of the plaintext.

7. A system comprising:

a host processor;

a host memory coupled to the host processor, the host memory to include a security operation, wherein the security operation includes a data cipher operation based on RC4, the host memory to include plaintext and a data structure for the data cipher operation;

a co-processor coupled to the host processor, the co-processor comprising,

an interface unit to retrieve the security operation from the host memory based on an instruction from the host processor;

an execution unit coupled to the interface unit, the execution unit comprising,

a memory to store the plaintext and the data structure associated with the data cipher operation;

a microcontroller unit to store the data cipher operation in an execution queue; and

an RC4 unit coupled to the execution queue, the RC4 unit to receive the data cipher operation, wherein the RC4 unit is to swap data stored in the S-box for data ciphering of a first portion of the plaintext and wherein the RC4 unit is to read data stored in the S-box for data ciphering of a second portion of the plaintext, prior to completion of the swapping of data stored in the S-box for data ciphering of the first portion of the plaintext, and wherein the RC4 unit is to swap data retrieved from the data structure for the data ciphering of the second portion of the plaintext upon determining that the data being swapped for the data ciphering of the first portion of the plaintext does not equal the data read from the data structure for data ciphering of the second portion of the plaintext.

8. The system of claim 7 , wherein the RC4 unit is to data cipher the second portion of the plaintext upon determining that the data being swapped in the data structure does not equal the data being read from the data structure.

9. The system of claim 7 , wherein the RC4 unit is to data cipher the first portion of the plaintext.

10. A machine-readable medium that provides instructions, which when executed by a machine, cause said machine to perform operations comprising:

receiving a request to perform data ciphering of plaintext; and

processing the request based on a data structure stored in a memory coupled to the processor, wherein the processing comprises,

performing a first access of data from the data structure;

swapping the data from the first access;

data ciphering a first portion of the plaintext based on the swapped data from the first access;

performing a second access of data from the data structure prior to the swapping of the data from the first access;

performing the following, upon determining that the data from the first access does not equal the data from the second access,

swapping the data from the second access; and

data ciphering a second portion of the plaintext based on the swapped data from the second access in an iteration including data ciphering a first portion of the plaintext based on the swapped data from the first access; and

performing the following, upon determining that the data from the first access equals data from the second access;

reexecuting the performing of the second access of data from the data structure in an iteration that is subsequent to determining that the data from the first access does not equal the data from the second access;

swapping the data from the second access; and

data ciphering the second portion of the plaintext based on the swapped data from the second access.

11. The machine-readable medium of claim 10 , wherein the data ciphering comprises an RC4 operation.

12. The machine-readable medium of claim 10 , wherein the data structure comprises a substitution-box.

13. The machine-readable medium of claim 10 , wherein processing the request for data ciphering of the plaintext comprises data ciphering the plaintext over a number of iterations and wherein the data ciphering of the first portion of the plaintext is in a same iteration as the data ciphering of the second portion of the plaintext.

Assignments (11)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
CHANGE OF NAME Recorded Jan 11, 2019
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 049367/0717 →
RELEASE OF SECURITY INTEREST Recorded Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
SECURITY AGREEMENT Recorded Aug 17, 2016
From: CAVIUM, INC.; CAVIUM NETWORKS LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039715/0449 →
MERGER Recorded Jul 18, 2011
From: CAVIUM NETWORKS, INC.
To: CAVIUM, INC.
Reel/Frame 026610/0478 →
RELEASE Recorded May 26, 2010
From: SILICON VALLEY BANK
To: CAVIUM NETWORKS INC
Reel/Frame 024445/0207 →
MERGER Recorded Feb 13, 2007
From: CAVIUM NETWORKS, A CALIFORNIA CORPORATION
To: CAVIUM NETWORKS, INC., A DELAWARE CORPORATION
Reel/Frame 018903/0354 →
SECURITY AGREEMENT Recorded Jan 8, 2003
From: CAVIUM NETWORKS
To: SILICON VALLEY BANK
Reel/Frame 013630/0621 →
INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Nov 6, 2002
From: CAVIUM NETWORKS
To: SILICON VALLEY BANK
Reel/Frame 013446/0927 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 7, 2002
From: CARLSON, DAVID A.
To: CAVIUM NETWORKS
Reel/Frame 012974/0068 →