Method and system for processing arbitration requests
View Patent ↗Method and system for arbitrating between plural arbitration requests is provided. The system includes a plurality of first stage arbiters that receive plural arbitration requests and a signal that indicates a previously granted request, wherein the first stage arbiters assert a high priority request signal if a high priority request is pending and a low priority request signal is asserted, if a low priority request is pending; a second stage arbiter that arbitrates between high priority requests, when high priority requests are pending; wherein if a high priority request is not pending, then a low priority request is granted; and a data handler module that operates in parallel with the second stage arbiter to immediately move data associated with a request that is granted at any given time.
1. An arbitration module for arbitrating between a plurality of arbitration requests, comprising:
a plurality of first stage arbiters that receive the plurality of arbitration requests and a signal that indicates a previously granted arbitration request, wherein each of the first stage arbiters, without granting any of the arbitration requests, asserts a high priority request signal if a high priority request is pending at said first stage arbiter and asserts a low priority request signal, if a low priority request is pending at said first stage arbiter;
a second stage arbiter that receives the high priority request signals and arbitrates between high priority requests, when high priority requests are pending at one or more of said first stage arbiters, wherein if a high priority request is not pending at any of said first stage arbiters, then a low priority request is granted by a low priority request handler; and
a data handler module that operates in parallel with the second stage arbiter to immediately move data associated with granted requests at any given time.
2. The arbitration module of claim 1 , wherein the of arbitration requests are to access a bus and/or memory location and are issued by direct access memory modules.
3. The arbitration module of claim 2 , wherein the data handler module includes a first stage data multiplexer and a second stage data multiplexer operating in parallel with the second stage arbiter, and the second stage data multiplexer selects data associated with a particular request after a request is granted.
4. The arbitration module of claim 1 , wherein an arbitration counter maintains a count of arbitration requests that are granted.
5. The arbitration module of claim 1 , wherein each first stage arbiter can process up to eight arbitration requests at one time.
6. The arbitration module of claim 1 , wherein if two requests are received from a same module back-to-back, then one is subtracted from an arbitration count to classify a back-to-back request as a high priority request.
7. The arbitration module of claim 6 , wherein a value of the arbitration count and a value that indicates whether a granted request falls within a particular group are sent to all first stage arbiters.
8. The arbitration module of claim 1 , wherein a host bus adapter uses the arbitration module to grant access to a host system memory.
9. A method for arbitrating between a plurality of arbitration requests, comprising:
receiving the plurality of requests and a signal that indicates a previously granted request at a plurality of first stage arbiters, wherein each of the first stage arbiters, without granting any of the arbitration requests, asserts a high priority request signal if a high priority request is pending at said first stage arbiter and asserts a low priority request signal if a low priority request is pending at said first stage arbiter;
receiving the high priority request signals at a second stage arbiter when high priority requests are pending at one or more of said first stage arbiters, wherein the second stage arbiter arbitrates between pending high priority requests;
sending a low priority request to a low priority request handler, wherein the low priority request is granted when no high priority requests are pending; and
transferring data associated with granted requests, wherein the data transfer occurs immediately after the request is granted via a data handler module that operates in parallel with the second stage arbiter.
10. The method of claim 9 , wherein the plurality of arbitration requests are to access a bus and/or memory location and are issued by direct access memory modules.
11. The method of claim 10 , wherein the data handler module includes a first stage data multiplexer and a second stage data multiplexer operating in parallel with the second stage arbiter, and the second stage data multiplexer selects data associated with a particular request as soon as the request is granted.
12. The method of claim 9 , wherein an arbitration counter maintains a count of arbitration requests that are granted.
13. The method of claim 9 , wherein each first stage arbiter can process up to eight arbitration requests at one time.
14. The method of claim 9 , wherein if two requests are received from a same module back-to-back, then one is subtracted from an arbitration count to classify a back-to-back request as a high priority request.
15. The method of claim 14 , wherein a value of the arbitration count and a value that indicates whether a granted request falls within a particular group are sent to all first stage arbiters.
16. The method of claim 9 , wherein a host bus adapter uses the arbitration module to grant access to a host system memory.