Data strobe generation
View Patent ↗In an embodiment, a method of generating strobe signals includes generating a first strobe signal in a first mode by operating a multiplexer with a clock signal to select between a first input signal and a second input signal, the first input signal having a static first signal level and the second input signal corresponding to a control signal. In a second mode, the method includes generating a second strobe signal by operating the multiplexer with the clock signal to select between the first input signal and the second input signal, the first input signal corresponding to the control signal inverted and delayed and the second input signal having a static second signal level.
1. A method of generating strobe signals, the method comprising:
operating a first multiplexer to select between a control signal and the control signal inverted and delayed;
generating a first strobe signal in a first memory circuit mode by operating a second multiplexer with a clock signal to select between a first input signal and a second input signal, the first input signal having a static first signal level and the second input signal corresponding to the control signal output by the first multiplexer; and
generating a second strobe signal in a second memory circuit mode by operating the second multiplexer with the clock signal to select between the first input signal and the second input signal, the first input signal corresponding to the control signal inverted and delayed output by the first multiplexer, and the second input signal having a static second signal level.
2. The method of claim 1 wherein the first memory circuit mode corresponds to a DDR3 memory circuit and the second memory circuit mode corresponds to a DDR4 memory circuit.
3. The method of claim 1 further comprising applying write leveling to the control signal prior to generating the first strobe signal in the first memory circuit mode.
4. The method of claim 1 further comprising applying write leveling to the control signal inverted and delayed prior to generating the second strobe signal in the second memory circuit mode.
5. The method of claim 1 wherein the static second signal level is inverted with respect to the static first signal level.
6. A strobe generation circuit comprising:
a first stage having a multiplexer configured in a first memory circuit mode to select a control signal and configured in a second memory circuit mode to select the control signal inverted and delayed; and
an other stage coupled to the first stage, the other stage having a multiplexer configured to select in the first memory circuit mode between a first input signal and a second input signal, the first input signal having a static first signal level and the second input signal corresponding to the control signal output by the multiplexer of the first stage, to generate a first strobe signal, the multiplexer configured to select in the second memory circuit mode between the first input signal and the second input signal, the first input signal corresponding to the control signal inverted and delayed output by the multiplexer of the first stage, and the second input signal having a static second signal level, to generate a second strobe signal.
7. The strobe generation circuit of claim 6 wherein the first memory circuit mode corresponds to a DDR3 memory circuit and the second memory circuit mode corresponds to a DDR4 memory circuit.
8. The strobe generation circuit of claim 6 further comprising a second stage coupled between the first stage and the other stage, the second stage configured to apply write leveling to the control signal prior to generating the first strobe signal in the first memory circuit mode and to apply write leveling to the control signal inverted and delayed prior to generating the second strobe signal in the second memory circuit mode.
9. The strobe generation circuit of claim 6 wherein the first stage receives the control signal from a memory controller.
10. The strobe generation circuit of claim 6 coupled between a memory controller and one or more memory components.
11. The strobe generation circuit of claim 6 wherein the static second signal level is inverted with respect to the static first signal level.
12. Apparatus comprising:
means for operating a multiplexer to select between a control signal and the control signal inverted and delayed;
means for generating a first strobe signal in a first memory circuit mode configured to select between a first input signal and a second input signal, the first input signal having a static first signal level and the second input signal corresponding to the control signal output by the multiplexer; and
means for generating a second strobe signal in a second memory circuit mode configured to select between the first input signal and the second input signal, the first input signal corresponding to the control signal inverted and delayed output by the multiplexer, and the second input signal having a static second signal level.
13. The apparatus of claim 12 wherein the first memory circuit mode corresponds to a DDR3 memory circuit and the second memory circuit mode corresponds to a DDR4 memory circuit.
14. The apparatus of claim 12 further comprising means for applying write leveling to the control signal prior to generating the first strobe signal in the first memory circuit mode.
15. The apparatus of claim 12 further comprising means for applying write leveling to the control signal inverted and delayed prior to generating the second strobe signal in the second memory circuit mode.
16. The apparatus of claim 12 wherein the static second signal level is inverted with respect to the static first signal level.