Apparatus and method for media access control scheduling with a sort hardware coprocessor

1. An apparatus, comprising:

a Media Access Control (MAC) scheduler that generates a sort request;

a hardware based sort coprocessor that services the sort request in accordance with specified packet processing priority parameters to generate a sorted array, wherein the hardware based sort coprocessor is configured to prioritize traffic based upon a priority parameter based on quality of service parameters, channel conditions, wait-in-queue time and timing efficiency;

a shared memory separate from and accessible by each of the MAC scheduler and the hardware based sort coprocessor, wherein the MAC scheduler generates a sort request that is written to the shared memory, wherein the sort request references a sort list, a number of elements to sort and a maximum number of sorted elements to return; and

the hardware based sort coprocessor accesses the sort request from the shared memory and operates to service the sort request.

2. The apparatus of claim 1 wherein the sorted array comprises sorted users for a mobile wireless communication system.

3. The apparatus of claim 1 wherein the sort coprocessor accesses a sort input array.

4. The apparatus of claim 1 wherein the MAC scheduler processes the sorted array to produce down link channel communications.

5. The apparatus of claim 1 wherein the sort coprocessor writes the sorted array to the memory and the MAC scheduler reads the sorted array from the memory.

6. A network node, comprising:

Layer-1 functional blocks;

Layer-2 functional blocks including

a Media Access Control (MAC) scheduler program executed on a processor that generates a sort request, and

a hardware based sort coprocessor that services the sort request in accordance with specified packet processing priority parameters to generate a sorted array, wherein the hardware based sort coprocessor is configured to prioritize traffic based upon a priority parameter based on quality of service parameters, channel conditions, wait-in-queue time and timing efficiency,

a shared memory separate from and accessible by each of the MAC scheduler and the hardware based sort coprocessor, wherein the MAC scheduler generates a sort request that is written to the shared memory, wherein the sort request references a sort list, a number of elements to sort and a maximum number of sorted elements to return, and

the hardware based sort coprocessor accesses the sort request from the shared memory and operates to service the sort request.

7. The network node of claim 6 wherein the MAC scheduler processes the sorted array to produce media access control blocks.

8. The network node of claim 6 wherein the hardware based sort coprocessor writes the sorted array to the memory and the MAC scheduler reads the sorted array from the memory.