System and method for improving dynamic range of analog-to digital converters
View Patent ↗An analog to digital converter (“ADC”) is provided that can be used in a system with an internal or external CPU or in an ASIC. The ADC includes a band gap reference (BGR) circuit whose output is internally coupled to an analog input of the ADC; and a positive analog supply voltage (AVDD) and a positive analog reference voltage (REFP) operationally coupled to a same voltage supply; wherein a BGR value is used by a CPU as a calibration constant for determining an AVDD value, a REFP value, and a Bit Weight value.
1. An analog to digital converter (“ADC”), comprising:
a band gap reference (BGR) circuit whose output is a direct analog input to the ADC;
a positive analog supply voltage (AVDD);
a positive analog reference voltage (REFP); and
a voltage supply operationally coupled to both the positive analog supply voltage (AVDD) and the positive analog reference voltage (REFP);
wherein a measured BGR value is used by a CPU as a calibration constant for determining an AVDD value.
2. The ADC of claim 1 , wherein the measured BGR value is used by the CPU as a calibration constant for determining a REFP value, and a Bit Weight value.
3. The ADC of claim 1 , wherein the measured BGR value is inversely proportional to the actual AVDD value.
4. A system using a CPU, comprising:
an analog to digital converter (“ADC”), wherein the ADC includes:
a band gap reference (BGR) circuit whose output is a direct analog input to the ADC;
a positive analog supply voltage (AVDD);
a positive analog reference voltage (REFP); and
a voltage supply operationally coupled to both the positive supply voltage (AVDD) and the positive analog reference voltage (REFP);
wherein a measured BGR value is used by the CPU as a calibration constant for determining an AVDD value.
5. The system of claim 4 , wherein the measured BGR value is used by the CPU as a calibration constant for determining a REFP value, and a Bit Weight value.
6. The system of claim 4 , wherein the measured BGR value is inversely proportional to the actual AVDD value.
7. An application specific integrated circuit (“ASIC”), comprising:
an analog to digital converter (“ADC”), comprising:
a band gap reference (BGR) circuit whose output is a direct analog input to the ADC;
a positive analog supply voltage (AVDD);
a positive analog reference voltage (REFP); and
a voltage supply operationally coupled to both the positive analog supply voltage (AVDD) and the positive analog reference voltage (REFP);
wherein a measured BGR value is used by a CPU as a calibration constant for determining an AVDD value.
8. The ASIC of claim 7 , wherein the measured BGR value is used by the CPU as a calibration constant for determining a REFP value, and a Bit Weight value.
9. The system of claim 7 , wherein the measured BGR value is inversely proportional to the actual AVDD value.