Self-triggering outgoing buffers
View Patent ↗A buffer output manager facilitates automatic self-triggering output of buffer contents. At least one processes writes control data to at least one buffer, the control data being such that a buffer output trigger address can be determined therefrom. For each buffer to which control data is written, a buffer output manager determines the trigger address of that buffer. At least one process writes data to at least one buffer, including to the trigger address thereof. For each buffer to which data is written to the trigger address, the buffer output manager automatically outputs the contents of that buffer, responsive to the writing of the data to the trigger address.
1. A method for self-triggering output of buffer contents, the method comprising:
writing, to at least one buffer, control data from which a buffer output trigger address can be determined; wherein the control data includes at least size information concerning the associated buffer;
for each buffer to which control data is written, determining a trigger address of that buffer from the control data;
writing data to the trigger address of at least one buffer; and
for each buffer to which data is written to the trigger address, automatically outputting contents of that buffer responsive to the writing of the data to the trigger address.
2. The method of claim 1 , further comprising:
writing control data to a plurality of buffers; and
writing data to the trigger addresses of a plurality of buffers; wherein at least some of the writing is performed in parallel.
3. The method of claim 1 further comprising:
outputting contents of buffers in an order in which data is written to the associated trigger addresses, using a first in-first out queue to maintain the order in which data is written to the associated trigger addresses.
4. The method of claim 1 further comprising:
writing a contiguous block of data to a plurality of contiguous addresses in the buffer, wherein the contiguous block of addresses includes the trigger address.
5. The method of claim 1 further comprising:
writing data to addresses in the buffer other than the trigger address; and
subsequently writing data to the trigger address to output contents of the buffer.
6. The method of claim 1 , further comprising:
a plurality of processes each writing control data and content to at least one buffer;
for each process of the plurality, outputting contents of buffers in an order in which data is written by that process to the associated trigger addresses, using a first in-first out queue to maintain the order in which data is written to the associated trigger addresses for each process.
7. The method of claim 1 wherein outputting contents of a buffer further comprises:
writing contents of the buffer to a destination as contiguous block of data.
8. A computer system for self-triggering output of buffer contents, the computer system comprising:
a portion configured to write, to at least one buffer, control data from which a buffer output trigger address can be determined, where the control data includes at least size information concerning the associated buffer;
a portion configured to, for each buffer to which control data is written, determine a trigger address of that buffer from the control data;
a portion configured to write data to the trigger address of at least one buffer; and
for each buffer to which data is written to the trigger address, a portion configured to automatically output contents of that buffer responsive to the writing of the data to the trigger address.
9. The computer system of claim 8 further comprising:
a portion configured to write control data to a plurality of buffers; and
a portion configured to write data to the trigger addresses of a plurality of buffers;
wherein the portions configured to write data to a plurality of buffers are further configured to write data to a plurality of buffers in parallel.
10. The computer system of claim 8 further comprising:
a portion configured to output contents of buffers in an order in which data is written to the associated trigger addresses, using a first in-first out queue to maintain the order in which data is written to the associated trigger addresses.
11. The computer system of claim 8 further comprising:
a portion configured to write a contiguous block of data to a plurality of contiguous addresses in the buffer, wherein the contiguous block of addresses includes the trigger address.
12. The computer system of claim 8 wherein the portion configured to write data to the trigger address of at least one buffer is further configured to:
write data to addresses in the buffer other than the trigger address; and
subsequently write data to the trigger address to output contents of the buffer.
13. The computer system of claim 8 wherein a plurality of processes each write control data and content to at least one buffer, the computer system further comprising:
a portion configured to output contents of buffers, for each process of the plurality, in an order in which data is written by that process to the associated trigger addresses, using a first in-first out queue, for each process of the plurality, to maintain the order in which data is written by that process to the associated trigger addresses.
14. The computer system of claim 8 further comprising;
a portion configured to write contents of the buffer to a destination as contiguous block of data.
15. A method for self-triggering output of buffer contents, the method comprising:
at least one buffer receiving control data from which a buffer output trigger address can be determined, wherein the control data includes at least size information concerning the associated buffer;
for each buffer which receives control data, determining a trigger address of that buffer from the control data;
at least one buffer receiving data at its trigger address; and
for each buffer which receives data at its trigger address, automatically outputting contents of that buffer responsive to a writing of the data to the trigger address.
16. The method of claim 15 further comprising:
a plurality of buffers receiving control data; and
a plurality of buffers receiving data at their trigger addresses.
17. The method of claim 15 further comprising:
outputting contents of buffers in an order in which data is received at the associated trigger addresses, using a first in-first out queue to maintain the order in which data is received at the associated trigger addresses.
18. The method of claim 15 further comprising:
receiving a contiguous block of data at a plurality of contiguous addresses in the buffer; wherein the contiguous block of addresses includes the trigger address.
19. The method of claim 15 further comprising:
receiving data at addresses in the buffer other than the trigger address; and
subsequently receiving data at the trigger address.
20. The method of claim 15 wherein at least one buffer receives data from a plurality of processes, the method further comprising
for each process of the plurality, outputting contents of buffers in an order in which data is received from that process at the associated trigger addresses, using a first in-first out queue to maintain the order in which data is received at the associated trigger addresses from that process.
21. The method of claim 15 wherein outputting contents of a buffer further comprises:
writing contents of the buffer to a destination as contiguous block of data.
22. An integrated circuit for self-triggering output of buffer contents, the integrated circuit comprising:
at least one buffer comprising a control data area and a data write area;
a portion configured to determine, from received control data, a trigger address of at least one buffer, the trigger address being located in the data write area, the portion configured to determine the trigger address being communicatively coupled to at least one buffer; and
a portion configured to automatically output buffer contents, responsive to a buffer receiving data at its trigger address, the portion configured to automatically output buffer contents being communicatively coupled to at least one buffer, and to the portion configured to determine the trigger address.
23. The integrated circuit of claim 22 further comprising:
a plurality of buffers, each buffer comprising a control data area and a data write area.
24. The integrated circuit of claim 22 wherein the portion configured to automatically output buffer contents is further configured to:
output contents of a plurality of buffers in an order in which data is received at the trigger addresses of the buffers, using a first in-first out queue configured to maintain the order in which data is received at the trigger addresses, the queue being communicatively coupled to the portion configured to automatically output buffer contents.
25. The integrated circuit of claim 22 wherein the portion configured to automatically output buffer contents is further configured to:
repeatedly output contents of a buffer in response to the buffer repeatedly
receiving data at its trigger address.