Granted Patent B1

US 9,009,364 · App. 14/142,643 · Granted Apr 14, 2015

Abstract

Claims (37)

1. A packet processor, comprising:

a packet memory manager configured to

store a page walk link list;

receive a descriptor;

initiate a page walk through the page walk link list in response to the descriptor and without a prompt from transmit direct memory access circuitry;

guarantee that the state of a first page of a packet is written by the time the descriptor of the packet is received;

apply a first latency to a second page of the packet, wherein the first latency is the difference between the latency of a packet processor ingress port to fill a full page with packet data and the maximum latency of a control block issuing a descriptor; and

apply a second latency to each additional page of the packet, wherein the second latency is the latency of the packet processor ingress port to fill a full page with packet data.

2. The packet processor of claim 1 wherein the packet memory manager is further configured to

receive an indicator of a single page packet; and

read a new packet in response to the indicator without waiting to obtain page state associated with the page of the single page packet.

3. The packet processor of claim 2 wherein the indictor is a single bit.

4. A packet processor, comprising:

a packet memory manager configured to

receive an indicator of a single page packet;

read a new packet in response to the indicator without waiting to obtain page state associated with the page of the single page packet;

guarantee that the state of a first page of a packet is written by the time a descriptor of the packet is received;

apply a first latency to a second page of the packet, wherein the first latency is the difference between the latency of a packet processor ingress port to fill a full page with packet data and the maximum latency of a control block issuing a descriptor; and

apply a second latency to each additional page of the packet, wherein the second latency is the latency of the packet processor ingress port to fill a full page with packet data.

5. The packet processor of claim 4 wherein the indictor is a single bit.

6. The packet processor of claim 4 , wherein the packet memory manager is further configured to

store a page walk link list;

receive a descriptor; and

initiate a page walk through the page walk link list in response to the descriptor and without a prompt from transmit direct memory access circuitry.

7. A packet processor, comprising:

a packet memory manager configured for cut-through operation so as to

guarantee that the state of a first page of a packet is written by the time the descriptor of the packet is received;

apply a first latency to a second page of the packet, wherein the first latency is the difference between the latency of a packet processor ingress port to fill a full page with packet data and the maximum latency of a control block issuing a descriptor; and

apply a second latency to each additional page of the packet, wherein the second latency is the latency of the packet processor ingress port to fill a full page with packet data.

8. The packet processor of claim 7 wherein the packet memory manager is further configured to

store a page walk link list;

receive a descriptor; and

initiate a page walk through the page walk link list in response to the descriptor and without a prompt from transmit direct memory access circuitry.

9. The packet processor of claim 7 wherein the packet memory manager is further configured to

receive an indicator of a single page packet; and

read a new packet in response to the indicator without waiting to obtain the page state associated with the page of the single page packet.

10. The packet processor of claim 9 wherein the indictor is a single bit.

Assignments (8)