IP Library Granted Patent US 9,128,769
Granted Patent B2
US 9,128,769 · App. 13/272,937 · Granted Sep 8, 2015

Processor with dedicated virtual functions and dynamic assignment of functional resources

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Quick Facts
Patent No.
US 9,128,769
App. No.
13/272,937
Granted
Sep 8, 2015
Kind
B2
Abstract

In one embodiment, a processor comprises a plurality of hardware resources, each hardware resource having a clock cycle. The processor also comprises a plurality of work stores, each work store assigned into one of a plurality of virtual functions if a mode of the processor is set to a virtual function mode, and each work store assigned into one physical function if the mode of the processor is set to a physical function mode. The processor further comprises dispatch logic configured to dispatch work from any work store corresponding to any virtual function or physical function to any released hardware resources.

Claims (32)

1. A method in a processor having a plurality of hardware resources comprising:

on at least one clock cycle:

setting a mode of the processor, the mode being one of a virtual function mode or a physical function mode;

if the mode of the processor is set to the virtual function mode, determining a plurality of virtual functions corresponding to the virtual function mode; wherein the virtual functions are configured to share the plurality of hardware resources among the plurality of virtual functions; and assigning each work store of a plurality of work stores into one of a plurality of virtual functions;

assigning the plurality of work stores into one physical function if the mode of the processor is set to the physical function mode;

on each clock cycle:

releasing any idle hardware resource to be available for any virtual function or physical function; and

dispatching work from any work store corresponding to any virtual function or physical function to any released hardware resources;

dispatching including arbitrating the work within each of the plurality of virtual functions to nominate corresponding work units and arbitrating among each of the corresponding work units to select a work unit for dispatch if the mode is set to the virtual function mode or arbitrating the work within the physical function to select a work unit for dispatch if the mode is set to the physical function mode.

2. The method of claim 1 , wherein the hardware resources include processing cores.

3. The method of claim 1 , wherein the work stores include instruction queues.

4. The method of claim 1 , wherein the virtual function can be a group of work stores, the group of work stores being at least one of eight work stores, sixteen work stores, thirty-two work stores, or sixty-four work stores.

5. The method of claim 1 , wherein dispatching work further comprises utilizing a plurality of work execution masks, each work execution mask corresponding to a work store and configured to permit or exclude the work from its corresponding work store from being assigned to any hardware resource as to affect the quality of service among the hardware resources and a utilizing plurality of group execution masks, each group execution mask corresponding to a class of work and configured to permit or exclude the class of work from being assigned to any hardware resource as to affect the quality of service among the hardware resources.

6. The method of claim 1 , wherein the physical function is configured to share the plurality of hardware resources among the work stores if the mode is physical function mode.

7. The method of claim 1 , wherein the virtual functions are further configured to share resources of the processor other than the plurality of hardware resources among the plurality of virtual functions.

8. A processor comprising:

a plurality of hardware resources, each hardware resource having a clock cycle;

wherein a mode of the processor can be set, the mode being one of a virtual function mode or a physical function mode;

a plurality of virtual functions corresponding to the virtual function mode;

wherein the virtual functions are configured to share the plurality of hardware resources if the mode of the processor is set to the virtual function mode;

a plurality of work stores, each work store assigned into one of a plurality of virtual functions if the mode of the processor is set to the virtual function mode, the plurality of work stores assigned into one physical function if the mode of the processor is set to the physical function mode;

wherein on each clock cycle, the plurality of hardware resources that are not processing work are released and available for any virtual function or physical function;

dispatch logic configured to dispatch work from any work store corresponding to any virtual function or physical function to any released hardware resources; and

an arbitration unit configured to arbitrate the work within each of the plurality of virtual functions to nominate corresponding work units and to arbitrate among each of the corresponding work units to select a work unit for dispatch if the mode is set to the virtual function mode or to arbitrate the work within the physical function to select a work unit for dispatch if the mode is set to the physical function mode.

9. The processor of claim 8 , wherein the hardware resources include processing cores.

10. The processor of claim 8 , wherein the work stores include instruction queues.

11. The processor of claim 8 , wherein the virtual function can be a group of work stores, the group of work stores being at least one of eight work stores, sixteen work stores, thirty-two work stores, or sixty-four work stores.

12. The processor of claim 8 , further comprising:

a plurality of work execution masks, each work execution mask corresponding to a work store and configured to permit or exclude the work from its corresponding work store from being dispatched to any hardware resource as to affect the quality of service among the hardware resources;

a plurality of group execution masks, each group execution mask corresponding to a class of work and configured to permit or exclude the class of work from being dispatched to any hardware resource as to affect the quality of service among the hardware resources.

13. The processor of claim 8 , wherein the virtual functions are configured to share the plurality of hardware resources if the mode of the processor is the virtual function mode, and the physical function is configured to share the plurality of hardware resources among the work stores if the mode is the physical function mode.

14. The processor of claim 8 , wherein the virtual functions are configured to share resources of the processor other than the plurality of hardware resources among the plurality of virtual functions.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
CERTIFICATE OF CONVERSION AND CERTIFICATE OF FORMATION Recorded Oct 2, 2018
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 047185/0422 →
RELEASE OF SECURITY INTEREST Recorded Jul 6, 2018
From: JP MORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: CAVIUM, INC; CAVIUM NETWORKS LLC; QLOGIC CORPORATION
Reel/Frame 046496/0001 →
SECURITY AGREEMENT Recorded Aug 17, 2016
From: CAVIUM, INC.; CAVIUM NETWORKS LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 039715/0449 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2012
From: SCHROEDER, JEFFREY; PANGBORN, JEFF; ANSARI, NAJEEB; CHIN, BRYAN; CHEN, LEO; SHAHID, AHMED; SCROBOHACI, PAUL; HU, CHEE; CARNS, MICHAEL; YE, WU; HUNTER, BRIAN
To: CAVIUM, INC.
Reel/Frame 027605/0628 →