Memory interface with selectable evaluation modes
View Patent ↗A memory interface enables AC characterization under test conditions without requiring the use of Automated Test Equipment (ATE) and functional patterns. The memory controller may be configured to generate output patterns through the test interface and create a loopback path for input specification testing using an external stressed-eye random number generator and checker. As a result, the memory interface may be evaluated for electrical and timing specifications under a relatively simple test setup and test procedure through the test interface (JTAG), as opposed to a complex processor program that sets up a similar memory access pattern on Automated Test Equipment (ATE).
1. A memory controller circuit comprising:
a pattern generator circuit configured to output a predetermined pattern signal;
a flip-flop configured to latch a received data signal at a first terminal of the memory controller circuit and output a looped-back latched data signal; and
a multiplexer configured to select among the pattern signal in a first mode of operation, the looped-back latched data signal in a second mode of operation, and a data output signal in a third mode of operation for output at a second terminal of the memory controller, the second terminal being connected to an external testing device in at least one of the first and second modes of operation and a memory device in the third mode of operation.
2. The circuit of claim 1 , wherein the memory controller is connected to a test load on a printed circuit board (PCB) at the first terminal.
3. The circuit of claim 2 , wherein the test load includes a resistor and a capacitor connected in series.
4. The circuit of claim 2 , wherein the memory controller further includes a third terminal, the third terminal alternating between operating as an output terminal during a WRITE operation and operating as an input terminal during a READ operation in the third mode of operation.
5. The circuit of claim 4 , wherein the memory controller is connected to an oscilloscope at the second and third terminals in the first mode of operation, the testing device including the oscilloscope.
6. The circuit of claim 4 , wherein the memory controller is connected to a BERTScope at the first, second and third terminal in the second mode of operation, the testing device including the BERTScope.
7. A method of testing a memory controller circuit comprising:
generating, at the memory controller circuit, a predetermined pattern signal;
latching, at the memory controller circuit, a received data signal at a first terminal of the memory controller circuit and outputting a looped-back latched data signal; and
selecting among the pattern signal in a first mode of operation, the looped-back latched data signal in a second mode of operation, and a data output signal in a third mode of operation for output at a second terminal of the memory controller, the second terminal being connected to an external testing device in the first and second modes of operation and a memory device in the third mode of operation.
8. The method of claim 7 , wherein the memory controller is connected to a test load on a printed circuit board (PCB) at the first terminal.
9. The method of claim 8 , wherein the test load includes a resistor and a capacitor connected in series.
10. The method of claim 8 , wherein the memory controller further includes a third terminal, the third terminal alternating between operating as an output terminal during a WRITE operation and operating as an input terminal during a READ operation in the third mode of operation.
11. The method of claim 10 , further comprising connecting the memory controller to an oscilloscope at the second and third terminals in the first mode of operation, the testing device including the oscilloscope.
12. The method of claim 10 , further comprising connecting the memory controller to a BERTScope at the first, second and third terminal in the second mode of operation, the testing device including the BERTScope.