Local ordering of instructions in a computing system
View Patent ↗A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.
1. A method for managing an observed order of instructions in a computing system, the method comprising:
executing a plurality of instructions at a first plurality of processor cores in the computing system, the executing including
issuing at least a first instruction of the plurality of instructions at a first processor core, the first instruction being configured to access resources associated with a second plurality of processor cores in the computing system; and
issuing a second instruction of the plurality of instructions at the first processor core, the second instruction causing the first processor core to pause issuance of further instructions for accessing resources in the computing system of the plurality of instructions until the first processor core receives one or more first acknowledgements that at least the first instruction of the plurality of instructions has reached a first location in circuitry of the first plurality of processor cores;
wherein the first processor core receives the one or more first acknowledgements before the first processor core receives a second acknowledgement that at least the first instruction of the plurality of instructions has reached a second location in circuitry of the second plurality of processor cores.
2. The method of claim 1 further comprising issuing at least a a third instruction of the plurality of instructions at a second processor core of the first plurality of processor cores, the third instruction configured to access the resources associated with the second plurality of processor cores, wherein at least the third instruction is constrained to issue after completion of the second instruction is observed by the first plurality of processor cores.
3. The method of claim 2 wherein the third instruction reaches the second location in circuitry of the second plurality of processor cores prior to the first instruction reaching the second location in circuitry of the second plurality of processor cores.
4. The method of claim 1 wherein the second instruction includes a memory barrier instruction.
5. The method of claim 1 wherein the first location in circuitry of the first plurality of processor cores includes a first ordering point from which the one or more first acknowledgements originate and the second location in circuitry of the second plurality of processor cores includes a second ordering point from which the second acknowledgement originates.
6. The method of claim 5 wherein instructions received at the first ordering point in a first received order are issued at the first plurality of processor cores in the first received order and instructions received at the second ordering point in a second received order are issued at the second plurality of processor cores in the second received order.
7. The method of claim 1 wherein at least some instructions of the plurality of instructions are memory access instructions.
8. The method of claim 7 wherein the at least some instructions of the plurality of instructions access memory addresses associated with memory mapped peripheral devices.
9. The method of claim 8 wherein the at least some instructions of the plurality of instructions access memory addresses associated with input/output devices.
10. The method of claim 9 wherein the first instruction is configured to access a memory address associated with an input/output device associated with the second plurality of processor cores.
11. The method of claim 1 wherein the first plurality of processor cores is associated with a first multi-element processing device located in a first CPU socket and the second plurality of processor cores is associated with a second multi-element processing device located in a second CPU socket.
12. The method of claim 1 wherein the first plurality of processor cores is associated with a first multi-element processing device located in a first CPU socket and the second plurality of processor cores is associated with the first multi-element processing device located in the first CPU socket.
13. The method of claim 1 wherein a first subset of the first plurality of processor cores is associated with a first multi-element processing device located in a first CPU socket and a second subset of the first plurality of processor cores is associated with a second multi-element processing device located in a second CPU socket.
14. The method of claim 13 wherein a first subset of the second plurality of processor cores is associated with the first multi-element processing device located in the first CPU socket and a second subset of the second plurality of processor cores is associated with the second multi-element processing device located in the second CPU socket.
15. The method of claim 1 further comprising executing a second plurality of instructions at a third plurality of processor cores in the computing system, the executing including
issuing at least a third instruction of the second plurality of instructions at a third processor core of the third plurality of processor cores, the third instruction being configured to access resources associated with a fourth plurality of processor cores in the computing system; and
issuing a fourth instruction of the second plurality of instructions at the third processor core, the fourth instruction causing the third processor core to pause issuance of further instructions for accessing resources in the computing system of the second plurality of instructions until the third processor core receives one or more third acknowledgements that at least the third instruction has reached a third location in circuitry of the third plurality of processor cores.
16. An apparatus for managing an observed order of instructions in a computing system, the apparatus comprising:
a first plurality of processor cores for executing a plurality of instructions, the first plurality of processor cores including a first processor core for:
issuing at least a first instruction of the plurality of instructions, the first instruction being configured to access resources associated with a second plurality of processor cores in the computing system; and
issuing a second instruction of the plurality of instructions, the second instruction causing the first processor core to pause issuance of further instructions for accessing resources in the computing system of the plurality of instructions until the first processor core receives one or more first acknowledgements that at least the first instruction of the plurality of instructions has reached a first location in circuitry of the first plurality of processor cores;
wherein the first processor core receives the one or more first acknowledgements before the first processor core receives a second acknowledgement that at least the first instruction of the plurality of instructions has reached a second location in circuitry of the second plurality of processor cores.
17. The apparatus of claim 16 wherein a second processor core of the first plurality of processor cores issues at least third instruction of the plurality of instructions, the third instruction configured to access the resources associated with the second plurality of processor cores, wherein at least the third instruction is constrained to issue after completion of the second instruction is observed by the first plurality of processor cores.
18. The apparatus of claim 17 wherein the third instruction reaches the second location in circuitry of the second plurality of processor cores prior to the first instruction reaching the second location in circuitry of the second plurality of processor cores.
19. The apparatus of claim 16 wherein the first location in circuitry of the first plurality of processor cores includes a first ordering point from which the one or more first acknowledgments originate and the second location in circuitry of the second plurality of processor cores includes a second ordering point from which the second acknowledgment originates.
20. The apparatus of claim 19 wherein instructions received at the first ordering point in a first received order are issued at the first plurality of processor cores in the first received order and instructions received at the second ordering point in a second received order are issued at the second plurality of processor cores in the second received order.