Local scratchpad and data caching system
View Patent ↗A RISC-type processor includes a main register file and a data cache. The data cache can be partitioned to include a local memory, the size of which can be dynamically changed on a cache block basis while the processor is executing instructions that use the main register file. The local memory can emulate as an additional register file to the processor and can reside at a virtual address. The local memory can be further partitioned for prefetching data from a non-cacheable address to be stored/loaded into the main register file.
1. A RISC processor, comprising:
a main register file that is accessed using instructions described by instruction mnemonics; and
a data cache, the data cache partitioned to include a local memory, the local memory residing at a virtual address within the data cache, the size of the local memory dynamically changed on a cache block basis while the processor is executing instructions that use the main register file;
wherein the local memory emulates as an additional register file to the processor and data is moved between the main register file and the additional register file using a single instruction described by the same instruction mnemonics;
wherein a single load/store instruction is used to move data between the local memory and the main register file.
2. The processor of claim 1 , wherein a load/store instruction has access to the virtual address of the local memory when the load/store instruction's effective virtual address matches the virtual address of the local memory.
3. The processor of claim 1 , wherein the single instruction utilizes a register in the main register file which gives a zero base address and the RISC processor has register base plus 16 -bit signed constant offset addressing.
4. The processor of claim 1 , wherein a load instruction uses r 0 in the main register file to store a base address.
5. The processor of claim 1 , wherein a data width for a data transfer to or from the local memory can be selected from a group consisting of 8-bits (byte), 16 bits (half-word), 32-bits (word), or 64-bits (double-word).
6. The processor of claim 5 , wherein the data is signed or unsigned.
7. The processor of claim 1 , wherein the local memory is further partitioned for prefetching data from a non-cacheable address to be stored/loaded into a main register file.
8. The processor of claim 7 , wherein the prefetched data includes multiple outstanding loads awaiting to be executed is loaded into the main register file.
9. The processor of claim 7 , wherein a delay instruction is used to guarantee the prefetched data is deposited into the local memory.
10. The processor of claim 1 , further including a plurality of processors.
11. The processor of claim 10 , wherein the plurality of processors comprise a network processor.
12. A method of partitioning a data cache, comprising:
accessing a main register file using instructions described by instruction mnemonics;
dynamically partitioning the data cache to include a local memory, the local memory residing at a virtual address within the data cache, the size of which can be changed on a cache block basis; and
wherein the local memory emulates as an additional register file to a processor and data is moved between the main register file and the additional register file using a single instruction described by the same instruction mnemonics;
wherein partitioning includes uniquely choosing an address to allow for a single load/store instruction used to move data between the local memory address and a main register file address.
13. The method of claim 12 , wherein access to a virtual address of the local memory is granted when a load/store instruction's effective virtual address matches the virtual address of the local memory.
14. The method of claim 12 , wherein the chosen address gives a value of zero and a negative offset.
15. The method of claim 12 , wherein a data width for a data transfer to or from the local memory can be selected from a group consisting of 8-bits (byte), 16 bits (half-word), 32-bits (word), or 64-bits (double-word).
16. The method of claim 15 , wherein the data can be signed or unsigned.
17. The method of claim 12 , further including partitioning the local memory for prefetching data from a non-cacheable address to be stored/loaded into a main register file.
18. The method of claim 17 , wherein the prefetched data includes multiple outstanding loads awaiting to be executed loaded into the main register file.
19. The method of claim 17 , wherein a delay instruction is used to guarantee the prefetched data is deposited into the local memory.
20. A partitioned data cache, comprising:
means for accessing a main register file using instructions described by instruction mnemonics;
means for dynamically partitioning a local memory of the data cache on a cache block basis, the local memory residing at a virtual address within the data cache; and
wherein the local memory emulates as an additional register file to a processor and data is moved between the main register file and the additional register file using a single instruction described by the same instruction mnemonics;
wherein a single load/store instruction is used to move data between the local memory and the main register file.