INSTRUCTION CACHE TRANSLATION MANAGEMENT
Managing an instruction cache of a processing element, the instruction cache including a plurality of instruction cache entries, each entry including a mapping of a virtual memory address to one or more processor instructions, includes: issuing, at the processing element, a translation lookaside buffer invalidation instruction for invalidating a translation lookaside buffer entry in a translation lookaside buffer, the translation lookaside buffer entry including a mapping from a range of virtual memory addresses to a range of physical memory addresses; causing invalidation of one or more of the instruction cache entries of the plurality of instruction cache entries in response to the translation lookaside buffer invalidation instruction.
1 . A method for managing an instruction cache of a processing element, the instruction cache including a plurality of instruction cache entries, each entry including a mapping of a virtual memory address to one or more processor instructions, the method comprising:
issuing, at the processing element, a translation lookaside buffer invalidation instruction for invalidating a translation lookaside buffer entry in a translation lookaside buffer, the translation lookaside buffer entry including a mapping from a range of virtual memory addresses to a range of physical memory addresses;
causing invalidation of one or more of the instruction cache entries of the plurality of instruction cache entries in response to the translation lookaside buffer invalidation instruction.
2 . The method of claim 1 further comprising determining the one or more instruction cache entries of the plurality of instruction cache entries including identifying instruction cache entries that include a mapping having a virtual memory address in the range of virtual memory addresses, wherein causing invalidation of one or more of the instruction cache entries includes invalidating each instruction cache entry of the one or more instruction cache entries.
3 . The method of claim 2 wherein each instruction cache entry includes a virtual address tag and determining the one or more instruction cache entries includes, for each instruction cache entry of the plurality of instruction cache entries, comparing the virtual address tag of the instruction cache entry to the range of virtual memory addresses.
4 . The method of claim 3 wherein comparing the virtual address tag of the instruction cache entry to the range of virtual memory addresses includes comparing the virtual address tag of the instruction cache entry to a portion of virtual memory addresses in the range of virtual memory addresses.
5 . The method of claim 3 wherein the portion of the virtual memory addresses includes a virtual page number of the virtual memory addresses.
6 . The method of claim 1 wherein causing invalidation of one or more of the instruction cache entries includes causing, at the processing element, an instruction cache entry invalidation operation.
7 . The method of claim 6 wherein the instruction cache entry invalidation operation is a hardware triggered operation.
8 . The method of claim 1 wherein the translation lookaside buffer invalidation instruction is a software triggered instruction.
9 . The method of claim 1 wherein causing invalidation of one or more of the instruction cache entries includes causing invalidation of an entirety of each of the one or more instruction cache entries.
10 . The method of claim 9 wherein causing invalidation of one or more of the instruction cache entries includes causing invalidation of all processor instructions associated with the one or more instruction cache entries.
11 . The method of claim 1 wherein causing invalidation of one or more of the instruction cache entries includes causing invalidation of a single processor instruction associated with the one or more instruction cache entries.
12 . The method of claim 1 wherein causing invalidation of one or more of the instruction cache entries includes causing invalidation of all of the instruction cache entries of the plurality of instruction cache entries.
13 . An apparatus comprising:
at least one processing element, including:
an instruction cache including a plurality of instruction cache entries, each entry including a mapping of a virtual memory address to one or more processor instructions, and
a translation lookaside buffer including a plurality of translation lookaside buffer entries, each entry including a mapping from a range of virtual memory addresses to a range of physical memory addresses;
wherein the processing element is configured to issue a translation lookaside buffer invalidation instruction for invalidating a translation lookaside buffer entry in the translation lookaside buffer; and
wherein the processing element is configured to cause invalidation of one or more of the instruction cache entries of the plurality of instruction cache entries in response to the translation lookaside buffer invalidation instruction.
14 . The apparatus of claim 13 wherein the processing element is configured to determine the one or more instruction cache entries of the plurality of instruction cache entries including identifying instruction cache entries that include a mapping having a virtual memory address in the range of virtual memory addresses, wherein causing invalidation of one or more of the instruction cache entries includes invalidating each instruction cache entry of the one or more instruction cache entries.
15 . The apparatus of claim 14 wherein each instruction cache entry includes a virtual address tag and determining the one or more instruction cache entries includes, for each instruction cache entry of the plurality of instruction cache entries, comparing the virtual address tag of the instruction cache entry to the range of virtual memory addresses.
16 . The apparatus of claim 15 wherein comparing the virtual address tag of the instruction cache entry to the range of virtual memory addresses includes comparing the virtual address tag of the instruction cache entry to a portion of virtual memory addresses in the range of virtual memory addresses.
17 . The apparatus of claim 15 wherein the portion of the virtual memory addresses includes a virtual page number of the virtual memory addresses.
18 . The apparatus of claim 13 wherein causing invalidation of one or more of the instruction cache entries includes causing, at the processing element, an instruction cache entry invalidation operation.
19 . The apparatus of claim 18 wherein the instruction cache entry invalidation operation is a hardware triggered operation.
20 . The apparatus of claim 13 wherein the translation lookaside buffer invalidation instruction is a software triggered instruction.
21 . The apparatus of claim 13 wherein causing invalidation of one or more of the instruction cache entries includes causing invalidation of an entirety of each of the one or more instruction cache entries.
22 . The apparatus of claim 21 wherein causing invalidation of one or more of the instruction cache entries includes causing invalidation of all processor instructions associated with the one or more instruction cache entries.
23 . The apparatus of claim 13 wherein causing invalidation of one or more of the instruction cache entries includes causing invalidation of a single processor instruction associated with the one or more instruction cache entries.
24 . The apparatus of claim 13 wherein causing invalidation of one or more of the instruction cache entries includes causing invalidation of all of the instruction cache entries of the plurality of instruction cache entries.