Method and system for data transfer
View Patent ↗Method and system for a data transfer operation to a device memory is provided. The method includes setting a counter to an initial value; detecting the data transfer operation; determining if information is written to a first memory location of the device memory; counting in a first direction when a total transfer size (N) is written to the first memory location of the device memory; and counting in a second direction when data is written in memory locations other than the first memory location of the device memory, wherein the data transfer operation is complete when a counter value transitions from a non-initial value to an initial value.
1. A system for indicating that a data transfer from a host system memory to a memory in a peripheral device is complete, comprising:
a counter associated with the memory in the peripheral device, the counter being set to an initial value, and being configured to count in a first direction when a value N representing a total size of the transfer from the host system memory is written to a first memory location of the peripheral device memory, the counter being further configured to count in a second direction when data is written in memory locations in the peripheral device other than the first memory location;
wherein when the value N is written to the first memory location the counter counts in the first direction a number equal to the value N; and
wherein the counter indicates that the data transfer is complete when the counter transitions from a non-initial value to the initial value.
2. The system of claim 1 , wherein the first direction is negative and the second direction is positive.
3. The system of claim 1 , wherein the first direction is positive and the second direction is negative.
4. The system of claim 1 , wherein the initial value is zero.
5. The system of claim 1 , wherein the total transfer size is written to the first memory location at a beginning, middle or end of the data transfer.
6. The system of claim 1 , wherein the first memory location is designated to store the transfer size information.
7. The system of claim 1 , wherein data is written from the host system memory to the peripheral device memory via an input/output bus.
8. A method for indicating that a data transfer from a host system memory to a memory in a peripheral device is complete, the method comprising the steps of:
setting a counter associated with the memory in the peripheral device to an initial value;
detecting the data transfer from the host system memory to the memory in the peripheral device;
determining if information is written to a first memory location of the peripheral device memory;
counting in a first direction when a value N representing a total size of the transfer is written to the first memory location of the peripheral device memory; and
counting in a second direction when data is written in memory locations in the peripheral device other than the first memory location of the peripheral device memory;
wherein when the value N is written to the first memory location the counter counts in the first direction a number equal to the value N; and
wherein the counter indicates that the data transfer is complete when the counter transitions from a non-initial value to the initial value.
9. The method of claim 8 , wherein the first direction is negative and the second direction is positive.
10. The method of claim 8 , wherein the first direction is positive and the second direction is negative.
11. The method of claim 8 , wherein the initial value is zero.
12. The method of claim 8 , wherein the total transfer size is written to the first memory location of the device memory at a beginning, middle or end of the data transfer.
13. The method of claim 8 , wherein the first memory location is designated to store the transfer size information.
14. The method of claim 8 , wherein data is written from the host system memory to the peripheral device memory via an input/output bus.