Synchronized clock phase interpolator
View Patent ↗A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.
1. A clock and data recovery (CDR) circuit comprising:
an interpolator circuit configured to receive a clock signal from a phase-locked loop and output a clock pair, the clock pair having a frequency matching a frequency of the clock signal including an in-phase signal and a quadrature-phase signal;
a divider configured to receive the clock pair and output a divided clock pair;
a pair of latches configured to clock a received data signal based on the divided clock pair;
a pair of deserializers configured to receive latched data signals from the pair of latches; and
a finite state machine connected to the outputs of the pair of deserializers, the finite state machine configured to compare the data latched by the in-phase clock signal against the data latched by the quadrature clock signal and to control the interpolator based on the comparison.
2. A method of recovering clock and data signals from an incoming serial data stream using a clock and data recovery (CDR) circuit and a reference clock generated by a variable oscillator, the method comprising:
generating a clock signal using a phase interpolator based on the reference clock and state information from a finite state machine (FSM), the phase interpolator operating at a fixed frequency;
generating a divided clock signal from the clock signal, the divided clock signal including an in-phase clock signal and a quadrature clock signal;
latching the data input according to the divided clock signal;
comparing the data latched by the in-phase clock signal against the data latched by the quadrature clock signal;
generating an updated phase interpolator state signal based on the comparison;
adjusting, via the phase interpolator state signal, phase and frequency of the recovered clock generated by the phase interpolator such that the latches clocked by the quadrature clock sample the input data at the center of the data eye; and
providing the FSM with updated phase and frequency information.
3. The method of claim 2 , wherein adjusting the phase and frequency causes the latches clocked by the in-phase clock to sample the input data at the data eye crossings.
4. The method of claim 3 , wherein the sample input data provides an indication of early and late edge information, the FSM receiving the information.
5. A clock and data recovery (CDR) circuit comprising:
an interpolator circuit configured to receive a clock signal from a phase-locked loop and output a clock pair;
a divider configured to receive the clock pair and output a divided clock pair, the divided clock pair having first and second clock signals;
a first and second pair of latches configured to clock a received data signal based on the divided clock pair, the first pair of latches being clocked by respective rising and falling edges of the first clock signal, the second pair of latches being clocked by respective rising and falling edge of the second clock signal;
a pair of deserializers configured to receive latched data signals from the pair of latches; and
a finite state machine connected to the outputs of the pair of deserializers, the finite state machine configured to compare the data latched by the first clock signal against the data latched by the second clock signal and to control the interpolator based on the comparison.
6. The circuit of claim 5 , wherein the first clock signal is a quadrature clock signal and the second clock signal is an in-phase clock signal.
7. The circuit of claim 6 , wherein the first pair of latches are configured to latch the input data at a center of a data eye, and wherein the second pair of latches are configured to latch the input data at a data eye crossing.
8. The circuit of claim 7 , wherein the first pair of latches output a recovered data signal, and wherein the second pair of latches indicate early and late edge information.
9. The circuit of claim 5 , wherein the divider is configured to output the divided clock pair having a frequency that is half a frequency of the received data signal.
10. The circuit of claim 5 , wherein the interpolator circuit is further configured to output the clock pair having a frequency matching a frequency of the clock signal.