Granted Patent B1

US 7,219,263 · App. 10/696,471 · Granted May 15, 2007

Abstract

Claims (27)

1. A system for minimizing memory corruption at power up and/or reset, comprising:

a digitally controlled potentiometer between an adapter and the memory; and

a voltage divider functionally coupled to the potentiometer.

2. The system of claim 1 , wherein the voltage divider includes a pull-down resistor that brings down the voltage at one of the plural potentiometer pins, minimizing the chances of memory corruption at power up and/or reset.

3. The system of claim 1 , wherein the potentiometer includes a wiper, which is stepped by an input up/down signal from the adapter.

4. The system of claim 1 , wherein the memory includes non-volatile random access memory.

5. A method for minimizing memory corruption at power up and/or reset, comprising:

setting a digitally controlled potentiometer to a resistance value such that upon power up and/or reset data cannot be written to the memory; and

setting the potentiometer in an increment or decrement mode such that resistance between plural pins of the potentiometer can be decreased or increased allowing content to be written to the memory after power up and/or reset.

6. The method of claim 5 , further comprising: enabling the memory for writing after toggling down the resistance between the plural potentiometer pins.

7. The method of claim 5 , wherein an up/down signal from an adapter toggles the resistance between the plural pins.

8. The method of claim 5 , wherein a voltage divider is functionally coupled to the potentiometer, such that upon power-up and/or reset, content cannot be written to the memory.

9. The method of claim 5 , wherein the memory includes non-volatile random access memory.

10. A circuit for minimizing memory corruption at power up and/or reset, comprising:

means for setting a digitally controlled potentiometer to a resistance value such that upon power up and/or reset data cannot be written to the memory; and

means for setting the potentiometer in an increment or decrement mode based on how the digitally controlled potentiometer has been configured such that resistance between plural pins of the potentiometer can be decreased or increased allowing content to be written to the memory after power up and/or reset.

11. The circuit of claim 10 , further comprising:

means for enabling the memory for writing after toggling resistance between the plural potentiometer pins.

12. The circuit of claim 10 , wherein an up/down signal from an adapter toggles the resistance between the plural pins.

13. The circuit of claim 10 , wherein a voltage divider is functionally coupled to the potentiometer, such that upon power-up and/or reset content cannot be written to the memory.

14. The circuit of claim 10 , wherein the memory includes non-volatile random access memory.

15. A system including a host bus adapter (HBA) coupled to a host system and a memory, comprising:

a digitally controlled potentiometer between the HBA and the memory; and

a voltage divider functionally coupled to the potentiometer wherein the voltage divider includes a pull-down resistor that brings down the voltage at one of the plural potentiometer pins, minimizing the chances of memory corruption.

16. The system of claim 15 , wherein the potentiometer is driven by signals from the adapter and is in increment or decrement mode upon power up and/or reset.

17. The system of claim 15 , wherein the potentiometer includes a wiper, which is stepped by an input up/down signal from the adapter.

18. The system of claim 15 , wherein the memory includes non-volatile random access memory.

Assignments (6)