Granted Patent B2

US 9,087,567 · App. 14/040,563 · Granted Jul 21, 2015

Abstract

Claims (49)

1. A method of calibrating an amplifier offset, the method comprising:

applying an input value to both input leads of an amplifier, the amplifier including one or more digital-to-analog converters (DACs) used to calibrate an offset of the amplifier;

updating, over a number of iterations by a control logic coupled to the amplifier, a digital value based on an output of the amplifier, the digital value updated being provided as input to a DAC of the one or more DACs in the amplifier; and

employing a final value of the digital value as input to the DAC of the one or more DACs in the amplifier for calibrating the offset of the amplifier during a data reception phase.

2. The method as recited in claim 1 , wherein the amplifier is within a single-ended receiver.

3. The method as recited in claim 2 , wherein the method of calibrating the amplifier offset is applied to multiple single-ended receivers of an input/output interface.

4. The method as recited in claim 3 , wherein the input/output interface is associated with a memory interface, the memory interface includes:

a double data rate 2 (DDR2) memory interface;

a double data rate 3 (DDR3) memory interface;

a double data rate 4 (DDR4) memory interface;

a low power double data rate 2 (LP DDR2) memory interface;

a low power double data rate 3 (LP DDR3) memory interface;

a low power double data rate 4 (LP DDR4) memory interface;

a graphical double data rate 3 (GDDR3) memory interface;

a graphical double data rate 4 (GDDR4) memory interface;

a graphical double data rate 5 (GDDR5) memory interface;

a wide input/output (Wide I/O) memory interface; or

a wide input/output 2 (Wide I/O 2) memory interface.

5. The method as recited in claim 1 , wherein the one or more DACs are coupled to at least one gain circuit in the amplifier.

6. The method as recited in claim 1 , wherein updating the digital value at a first iteration includes determining the DAC, from the one or more DACs, associated with the digital value.

7. The method as recited in Claim 1 , wherein determining the DAC associated with the digital value includes determining the DAC based on the output of the amplifier and a coupling of the DAC to a gain circuit in the amplifier.

8. The method as recited in claim 1 , wherein updating the digital value based on the output of the amplifier includes updating the digital value based on an indication of whether the output of the amplifier is greater or less than zero.

9. The method as recited in claim 1 , wherein the digital value is represented by multiple bits.

10. The method as recited in claim 1 , wherein the number of iterations is equal to a number of bits representing the digital value.

11. A system for calibrating an amplifier offset comprising:

an amplifier including one or more digital-to-analog converters (DACs) with corresponding input used to calibrate an offset of the amplifier; and

a control logic coupled to the amplifier configured to update, over a number of iterations, a digital value based on an output of the amplifier, the digital value updated being provided as input to a DAC of the one or more DACs in the amplifier,

a final value of the digital value updated being employed as input to the DAC of the one or more DACs in the amplifier for calibrating the offset of the amplifier during a data reception phase.

12. The system as recited in claim 11 , wherein the amplifier is within a single-ended receiver.

13. The system as recited in claim 12 , wherein the system is configured to calibrate the amplifier offset for multiple single-ended receivers of an input/output interface.

14. The system as recited in claim 13 , wherein the system further includes a multiplexer configured to serially combine outputs from multiple amplifiers associated with the multiple single-ended receivers into a single output signal, the control logic being further configured to update an input digital value for each amplifier based the corresponding output of the amplifier in the single output signal.

15. The system as recited in claim 13 , wherein the input/output interface is associated with a memory interface, the memory interface includes:

a double data rate 2 (DDR2) memory interface;

a double data rate 3 (DDR3) memory interface;

a double data rate 4 (DDR4) memory interface;

a low power double data rate 2 (LP DDR2) memory interface;

a low power double data rate 3 (LP DDR3) memory interface;

a low power double data rate 4 (LP DDR4) memory interface;

a graphical double data rate 3 (GDDR3) memory interface;

a graphical double data rate 4 (GDDR4) memory interface;

a graphical double data rate 5 (GDDR5) memory interface;

a wide input/output (Wide I/O) memory interface; or

a wide input/output 2 (Wide I/O 2) memory interface.

16. The system as recited in claim 11 , wherein the one or more DACs are coupled to at least one gain circuit in the amplifier.

17. The system as recited in claim 11 , wherein in updating the digital value at a first iteration, the control logic is further configured to determine the DAC, from the one or more DACs, associated with the digital value.

18. The system as recited in claim 17 , wherein in determining the DAC associated with the digital value, the control logic is further configured to determine the DAC based on the output of the amplifier and a coupling of the DAC to a gain circuit in the amplifier.

19. The system as recited in claim 11 , wherein the system further includes a comparator configured to determine whether the output of the amplifier is logic 1 or 0, the control logic being further configured to update the digital value based on whether the output of the amplifier is logic 1 or 0.

20. The system as recited in claim 11 , wherein the digital value is represented by multiple bits.

21. The system as recited in claim 11 , wherein the number of iterations is equal to a number of bits representing the digital value.

Assignments (6)