State machine for deskew delay locked loop
View Patent ↗A state machine for a DLL ensures a given clock (DCLK) is always locked to the rising edge of an incoming reference clock (REFCLK) through the use of two additional phase detectors. The first phase detector samples the value of DCLK a given delay prior to the rising edge of REFCLK, and the second samples the value of DCLK a given delay after the rising edge of REFCLK. The additional information provided by these two phase detectors enables a determination as to whether we are close to the falling edge of REFCLK, and, if so, add enough delay to DCLK to ensure that the DLL locks only to the rising edge of REFCLK and never accidentally to the falling edge.
1. A deskew DLL circuit comprising:
a delay line configured to receive a clock signal input and output a delayed clock signal;
a first phase detector configured to compare the delayed clock signal against a reference clock;
a second phase detector configured to compare the delayed clock signal against a delayed version of the reference clock;
a third phase detector configured to compare a delayed version of the delayed clock signal against the reference clock; and
a control block configured to control a delay of the delay line based on outputs of the first, second and third phase detectors;
wherein the control block further comprises a state machine configured to determine a proximity of a rising edge of the clock signal to an edge of the reference clock, the state machine controlling the delay line based on whether the edge of the reference clock is a rising edge or a falling edge.
2. The circuit of claim 1 , wherein the state machine is configured to determine the proximity based on at least one of the outputs of the first, second and third phase detectors.
3. The circuit of claim 1 , wherein the state machine is configured to transition from an initial state to a selected state based on the output of at least two of the outputs of the first, second and third phase detectors.
4. The circuit of claim 3 , wherein the at least two of the outputs include the outputs of the second and third phase detectors.
5. The circuit of claim 1 , wherein the state machine is configured to transition to a locked state based on the output of the first phase detector.
6. The circuit of claim 1 , wherein the state machine, based on the outputs of the second and third phase detectors, is configured to transition to a state whereby the delayed clock signal is incremented a fixed number of delay units.
7. The circuit of claim 1 , wherein the control block is configured to control the delay of the delay line to lock an edge of the delayed clock signal to an edge of the reference clock.
8. The circuit of claim 7 , wherein the edge of the delayed clock signal and the edge of the reference clock are rising edges.
9. The circuit of claim 7 , wherein the edge of the delayed clock signal and the edge of the reference clock are falling edges.
10. A deskew DLL circuit comprising:
a delay line configured to receive a clock signal input and output a delayed clock signal;
a first phase detector configured to compare the delayed clock signal against a reference clock;
a second phase detector configured to compare the delayed clock signal against a delayed version of the reference clock;
a third phase detector configured to compare a delayed version of the delayed clock signal against the reference clock; and
a control block configured to control a delay of the delay line based on outputs of the first, second and third phase detectors;
wherein the delayed clock signal has a frequency being a submultiple of the reference clock.
11. A deskew DLL circuit comprising:
a delay line configured to receive a clock signal input and output a delayed clock signal;
a first phase detector configured to compare the delayed clock signal against a reference clock;
a second phase detector configured to compare the delayed clock signal against a delayed version of the reference clock;
a third phase detector configured to compare a delayed version of the delayed clock signal against the reference clock; and
a control block configured to control a delay of the delay line based on outputs of the first, second and third phase detectors;
wherein the reference clock has a frequency being a submultiple of the delayed clock signal.