Debug interface for multiple CPU cores

1. A system, comprising:

resources within processor cores that are each in communication with a debug bus such that the cores receive packets over the debug bus,

the cores executing transactions in response to the packets,

the packets each being a type of packet selected from a group that includes Second Access Bus (SAB) packets and Debug Access Bus (DAB) packets,

the resources including specified resources and non-specified resources,

a core that executes a transaction in response to a DAB packet accesses a specified resource and a core that executes a transaction in response to a SAB packet accesses a non-specified resource,

a debug specification identifies the specified resources as being accessible by a debug controller but does not identify the non-specified resources as being accessible by the debug controller.

2. The system of claim 1 , wherein the cores are based on reduced instruction set computing (RISC) architectures.

3. The system of claim 2 , wherein the cores are based on an Advanced RISC Machine (ARM) specification.

4. The system of claim 1 , wherein the debug specification is the Advanced RISC Machine (ARM) debug interface specification.

5. The system of claim 1 , wherein the resources are debug registers.

6. The system of claim 1 , wherein the cores each serve as a node of a loop network.

7. The system of claim 6 , further comprising: the debug controller, the debug controller being a node on the loop network.

8. The system of claim 1 , wherein the debug bus is a serial bus.

9. The system of claim 8 , wherein the debug bus includes fewer wires than a number of bits in the largest packet selected from the group consisting of the DAB packet and the SAB packet.

10. The system of claim 1 , wherein the de-bug bus is a one-wire bus.

11. The system of claim 9 , wherein the packets include one or more bits in a packet type field, the one or more bits indicating whether the packet is DAB packet or a SAB packet.

12. The system of claim 1 , further comprising: the debug controller, the debug controller placing the packets on the debug bus.

13. The system claim 12 , wherein the debug controller places a packet on the debug bus in response to receiving a request from one or more of the cores.

14. The system claim 12 , wherein the debug controller places a packet on the debug bus in response to receiving a request from one or more external debug agents.

15. The system claim 12 , wherein the debug controller places packets on the debug bus in response to receiving requests from one or more of the cores, the debug controller rejecting a portion of the request and executing another portion of the requests in accordance with one or more security mechanisms.

16. The system of claim 15 , wherein the debug controller rejects requests from a core operating in a non-secure state where a secure resource is accessed as a result of executing the request.

17. The system of claim 16 , wherein the debug controller executes at least a portion of the requests from a core operating in a secure state where a secure resource is accessed as a result of executing the request and also executes at least a portion of the requests from a core operating in a secure state where a non-secure resource is accessed as a result of executing the request.

18. The system of claim 1 , wherein the cores execute transactions in response to receiving packets on the debug bus, the transactions including read transactions and write transactions.

19. The system of claim 18 , wherein the transactions include a poll transaction where each core modifies the same packet as the packet passes through the loop network.

20. The system of claim 19 , wherein the modified packet is returned to a debug controller that acts as one of the nodes in the loop network.

21. The system of claim 19 , wherein each core modifies that modifies the packet modifies a different portion of the packet.

22. The system of claim 21 , wherein the portion of the packet that is modified by a core is associated with that core.

23. The system of claim 18 , wherein the transactions include a broadcast transaction, the cores executing the broadcast transactions in response to receiving a broadcast packet and each core that receives the broadcast packet performs a write operation in response to receiving the broadcast packet.

24. The system of claim 23 , wherein data written as part of the write operation is the same for each core that receives the broadcast packet.

25. The system of claim 23 , wherein the broadcast packet is returned to a debug controller that acts as one of the nodes in the loop network.

26. A debugging method, comprising:

employing a Debug Access Bus (DAB) to access specified resources from within processor cores that are each in communication with a debug bus; and

employing a Second Access Bus (SAB) to access non-specified resources within the processor cores,

the debug bus being a physical bus and the DAB and the SAB each being a logical bus on the debug bus,

the specified resources each being a resource that a debug specification identifies as being accessible by a debug controller, and

the non-specified resources each being a resource that the debug specification does not identify as being accessible by the debug controller.

27. The method of claim 26 , wherein the cores are based on reduced instruction set computing (RISC) architectures.

28. The method of claim 26 , wherein the cores are based on an Advanced RISC Machine (ARM) debug interface architectures.

29. The method of claim 26 , wherein the debug specification is the Advanced RISC Machine (ARM) debug interface specification.

30. The method of claim 26 , wherein the cores each serve as a node of a loop network.