Phase measurement and correction circuitry
A circuit provides for phase adjustment of an offset clock pair, and includes an analog stage and a digital stage. The analog stage provides for generating an adjusted offset clock pair and detecting a phase difference between the adjusted offset clock pair. The digital stage operates to quantify the phase difference and provide a command for further adjusting the phase of the adjusted offset clock pair, at the analog stage, towards a target phase offset value.
1. A circuit comprising:
a phase adjustment circuit configured to receive an offset clock pair and output an adjusted offset clock pair, and
a phase detector configured to receive the adjusted offset clock pair and output a phase signal, the phase signal indicating a phase difference between the adjusted offset clock pair;
an analog-to-digital converter configured to receive the phase signal and output a digital phase value corresponding to the phase signal; and
a comparator configured to output an error value based on a comparison of the digital phase value against a reference value, and
an integrator configured to output a phase adjustment value based on the error value, the phase adjustment circuit adjusting at least one phase of the adjusted offset clock pair based on the phase adjustment value.
2. The circuit of claim 1 , further comprising a summer circuit configured to generate a phase adjust signal based on the phase adjustment value and an initial value, the phase adjustment circuit receiving the phase adjustment signal.
3. The circuit of claim 1 , wherein the phase adjustment circuit is further configured to adjust the at least one phase of the adjusted offset clock pair towards a phase difference between the adjusted offset clock pair of 90°.
4. The circuit of claim 1 , wherein the phase adjustment circuit includes a first interpolator and a second interpolator, the first interpolator receiving a first clock signal of the offset clock pair, the second interpolator receiving a second clock signal of the offset clock pair.
5. The circuit of claim 4 , wherein at least one of the first and second interpolators is further configured to output one of the adjusted offset clock pair based on at least one of the offset clock pair and the phase adjustment value.
6. The circuit of claim 1 , wherein the phase detector includes a symmetric exclusive-OR (XOR) gate, the symmetric XOR gate receiving the adjusted offset clock pair and outputting the phase signal.
7. The circuit of claim 6 , wherein the phase signal includes at least one clock signal having a duty cycle indicating the phase difference between the adjusted offset clock pair.
8. The circuit of claim 1 , wherein the analog-to-digital converter includes a sigma-delta analog-to-digital converter configured to output the digital phase value as a low-pass-filtered version of the phase signal.
9. The circuit of claim 1 , wherein the reference value includes a tolerance value.
10. The circuit of claim 1 , wherein the integrator includes an up-down counter, the counter incrementing and decrementing the up-down counter based on the error value.
11. The circuit of claim 1 , further comprising a first stage and a second stage, the first stage including the phase adjustment circuit and the phase detector, the second stage including the comparator and the integrator.
12. The circuit of claim 11 , wherein the first stage is an analog stage and the second stage is a digital stage.
13. A clock recovery circuit comprising:
a receiver configured to sample an input data signal based on an adjusted offset clock pair;
a clock and data recovery (CDR) circuit configured to generate a recovered data signal based on the input data signal, the CDR circuit further generating an offset clock pair; and
a clock adjustment circuit including:
a phase adjustment circuit configured to receive the offset clock pair and output the adjusted offset clock pair,
a phase detector configured to receive the adjusted offset clock pair and output a phase signal, the phase signal indicating a phase difference between the adjusted offset clock pair,
an analog-to-digital converter configured to receive the phase signal and output a digital phase value corresponding to the phase signal,
a comparator configured to output an error value based on a comparison of the digital phase value against a reference value, and
an integrator configured to output a phase adjustment value based on the error value, the phase adjustment circuit adjusting at least one phase of the adjusted offset clock pair based on the phase adjustment value.
14. The circuit of claim 13 , wherein the clock adjustment circuit includes an analog stage and a digital stage, the analog stage including the phase adjustment circuit and the phase detector, the digital stage including the comparator and the integrator.
15. The circuit of claim 13 , further comprising a phase-locked loop (PLL), the CDR circuit generating the offset clock pair based on an output of the PLL.
16. A clock distribution circuit comprising:
a clock generator configured to output an offset clock pair;
a clock distribution bus connected to the clock generator; and
a plurality of clock adjustment circuits each configured to receive the offset clock pair, via the clock distribution bus, and output an adjusted offset clock pair to a respective receiver circuit, each of the plurality of clock adjustment circuits including:
a phase adjustment circuit configured to receive the offset clock pair and output the adjusted offset clock pair,
a phase detector configured to receive the adjusted offset clock pair and output a phase signal, the phase signal indicating a phase difference between the adjusted offset clock pair,
an analog-to-digital converter configured to receive the phase signal and output a digital phase value corresponding to the phase signal,
a comparator configured to output an error value based on a comparison of the digital phase value against a reference value, and
an integrator configured to output a phase adjustment value based on the error value, the phase adjustment circuit adjusting at least one phase of the adjusted offset clock pair based on the phase adjustment value.
17. The circuit of claim 16 , wherein the clock adjustment circuit includes an analog stage and a digital stage, the analog stage including the phase adjustment circuit and the phase detector, the digital stage including the comparator and the integrator.
18. The circuit of claim 16 , wherein each of the plurality of clock adjustment circuits is further configured to output the respective adjusted clock pair at a phase that is distinct from a phase of at least one other adjusted clock pair.