IP Library Granted Patent US 10,740,256
Granted Patent B2
US 10,740,256 · App. 15/602,620 · Granted Aug 11, 2020

Re-ordering buffer for a digital multi-processor system with configurable, scalable, distributed job manager

Inventors: Kalyana Sundaram Venkataraman (Santa Clara, CA); Jason Daniel Zebchuk (Watertown, MA); Gregg Alan Bouchard (Georgetown, TX); Tejas Maheshbhai Bhatt (Sunnyvale, CA); Hong Jik Kim (San Jose, CA); Eric Marenger (Montreal, CA); Ahmed Shahid (San Jose, CA)
Assignee: Marvell Asia Pte, Ltd.
G06F13/1626G06F9/5016G06F9/524G06F12/023G06F13/1663G06F13/1673G06F9/4881G06F9/5083
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Quick Facts
Patent No.
US 10,740,256
App. No.
15/602,620
Granted
Aug 11, 2020
Kind
B2
Abstract

A method utilizing a system encompassing a free pool buffer; a deadlock avoidance buffer; and a controller communicatively coupled to the free pool buffer and the deadlock avoidance buffer to reorder out-of-order responses to fetch requests into correct order by: receiving a fetch request on behalf of a consumer; allocating space first in the free pool buffer and when such space is not available then allocating space in a division associated with the consumer in the deadlock avoidance buffer. Issuing segment(s) of the fetch request including associated tag(s) to one of one or more memories; writing response data for each of the segment(s) to the allocated space in the free buffer or the deadlock avoidance buffer according to each of the associated tag(s); and transferring the response data to the consumer according to an entry in an ordering first-in, first-out buffer and an entry in a pending request array.

Claims (58)

1. An apparatus for reordering out-of-order information provided by one or more memories into correct order, comprising:

a free pool buffer comprising a first logical memory structure;

a deadlock avoidance buffer comprising a second logical memory structure; and

a controller communicatively coupled to the free pool buffer and the deadlock avoidance buffer.

2. The apparatus as claimed in claim 1 , wherein the first logical memory structure is configured to be divisible into a plurality of entries, wherein:

each entry comprises a group,

each group comprises at least one item, and

each item comprises at least one configuration word.

3. The apparatus as claimed in claim 2 , wherein the plurality of entries are allocated to consumers on per needed basis.

4. The apparatus as claimed in claim 2 , wherein a size of the group comprises:

a size equal to a simple proper fraction of a largest access size of the one or more memories.

5. The apparatus as claimed in claim 1 , wherein:

the second logical memory structure comprises a plurality of divisions.

6. The apparatus as claimed in claim 5 , wherein the plurality of divisions comprises:

a number of divisions equal to a number of consumers.

7. The apparatus as claimed in claim 5 , wherein the plurality of divisions comprises:

a number of divisions equal to a number of active consumers.

8. The apparatus as claimed in claim 5 , wherein each of the plurality of divisions is configured to be divisible into at least one group, wherein:

each of the at least one group comprises at least one item, and

each of the at least one item comprises at least one configuration word.

9. The apparatus as claimed in claim 8 , wherein a size of each of the at least one group comprises:

a size equal to a simple proper fraction of a largest access size of the one or more memories.

10. The apparatus as claimed in claim 1 , wherein the controller comprises:

a third logical memory structure organized into a plurality of ordering first-in-first-out buffers, wherein each of the plurality of ordering first-in-first-out buffers is associated with one of the plurality of consumers;

a fourth logical memory structure organized into a plurality of pending request arrays, wherein each of the plurality of pending request arrays is associated with one of the plurality of consumers; and

a controller logic communicatively coupled to the third logical memory structure and the fourth logical memory structure.

11. The apparatus as claimed in claim 10 , wherein the controller further comprises:

a lookup table communicatively coupled to the third logical memory structure and the fourth logical memory structure.

12. A method for reordering out-of-order responses to fetch requests from one or more memories into correct order, comprising:

receiving a fetch request on behalf of a consumer;

determining whether there is space in a free pool buffer, and when the determination is positive then allocating the space equal to a size of a group in the free pool buffer;

else determining whether there is space in a division in a deadlock avoidance buffer assigned to the consumer that generated the fetch request, and when the determination is positive then allocating the space equal to a size of a group in the division;

creating an entry representing the group in an ordering first-in, first-out buffer associated with the consumer and an entry representing the group in a pending request array associated with the consumer;

issuing at least one segment of the fetch request comprising an associated tag to one of the one or more memories;

writing response data for each of the at least one segment of the fetch request to the allocated space in the free buffer or the deadlock avoidance buffer in accordance with each of the associated tag;

updating the entry in the pending request array in accordance with the response data; and

transferring the response data to the consumer in accordance with the entry in the ordering first-in, first-out buffer and the entry in the pending request array.

13. The method as claimed in claim 12 , wherein the deadlock avoidance buffer comprises a number of divisions equal to a number of consumers.

14. The method as claimed in claim 12 , wherein the size of the group equals a simple proper fraction of the largest access size of the one or more memories.

15. The method as claimed in claim 12 , wherein the issuing at least one segment of the fetch request comprising an associated tag to one of the one or more memories comprises:

determining a number of segments of the fetch request in accordance with an access size of the one or more memories, the size of the group, and a size of data to be fetched; and

issuing the determined number of the segments of the fetch request.

16. The method as claimed in claim 12 , further comprising:

allocating at least one entry in a lookup table;

writing each of the associated tag into one of the at least one allocated entry;

providing an identifier for each of the at least one allocated entry in the lookup table; and

using the provided identifier as the associated tag.

17. The method as claimed in claim 12 , wherein the updating the entry in the pending request array in accordance with the response data comprises:

subtracting a size of the response data from a size of data remaining to be fetched; and

updating the entry in the pending request array with a result of the subtraction.

18. The method as claimed in claim 12 , wherein the transferring the response data to the consumer in accordance with the entry in the ordering first-in, first-out buffer and the entry in the pending request array comprises:

determining in accordance with the entry in the pending request array whether a size of data equal to the size of the group have been returned;

determining whether a head entry of the ordering first-in, first-out buffer is non-empty; and

transferring the response data when both the determinations are positive.

19. The method as claimed in claim 18 , wherein transferring the response data when both the determinations are positive comprises:

determining for each item of the response data an offset; and

transferring for each item a portion of the item identified by the offset.

20. The method as claimed in claim 16 , wherein the writing response data for each of the at least one fetch request to the allocated space in the free buffer or the deadlock avoidance buffer in accordance with each of the associated tag comprises: separating the response data from the provided identifier; retrieving the associated tag in accordance with the identifier; and writing the response data to the allocated space in the free buffer or the deadlock avoidance buffer in accordance with the associated tag.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053179/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2020
From: CAVIUM, LLC
To: CAVIUM INTERNATIONAL
Reel/Frame 051948/0807 →
CHANGE OF NAME Recorded Dec 12, 2019
From: CAVIUM, INC.
To: CAVIUM, LLC
Reel/Frame 051260/0567 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2017
From: VENKATARAMAN, KALYANA SUNDARAM; ZEBCHUK, JASON DANIEL; BOUCHARD, GREGG ALAN; BHATT, TEJAS MAHESHBHAI; KIM, HONG JIK; MARENGER, ERIC; SHAHID, AHMED
To: CAVIUM, INC.
Reel/Frame 043276/0895 →
Continuity (1)
Related Publication 20180341602A1 · Nov 29, 2018