Method and apparatus for using multiple linked memory lists
An apparatus and method for queuing data to a memory buffer. The method includes selecting a queue from a plurality of queues; receiving a token of data from the selected queue and requesting, by a queue module, addresses and pointers from a buffer manager for addresses allocated by the buffer manager for storing the token of data. Subsequently, a memory list is accessed by the buffer manager and addresses and pointers are generated to allocated addresses in the memory list which comprises a plurality of linked memory lists for additional address allocation. The method further includes writing into the accessed memory list the pointers for the allocated address where the pointers link together allocated addresses; and migrating to other memory lists for additional address allocations upon receipt of subsequent tokens of data from the queue; and generating additional pointers linking together the allocated addresses in the other memory lists.
1. A method performed by a buffer manager to queue data to a memory buffer, the method comprising:
receiving a request for addresses and pointers for addresses allocated by the buffer manager, for storing a set of tokens of data from a queue selected from a plurality of queues, wherein the set of tokens of data comprises more than two tokens of data;
accessing a memory list, and generating the addresses and the pointers to allocated addresses in the memory list, wherein the memory list comprises more than two parallel linked memory lists;
writing the pointers for the allocated addresses into the memory list to form a set of more than two linked memory locations, wherein each memory location of the set of more than two linked memory locations is allocated in a distinct parallel linked memory list in the more than two parallel linked memory lists, wherein the pointers externally link together each memory location of the set of more than two linked memory locations, and wherein each of the more than two parallel linked memory lists is divided into more than two memory locations; and
migrating to another set of more than two linked memory locations for additional address allocations upon receipt of another set of tokens of data from the queue, and generating additional pointers linking together memory locations of the other set of more than two linked memory locations.
2. The method of claim 1 , further comprising generating tail pointers and head pointers that link more than two allocated addresses of the set of tokens of data across the more than two parallel linked memory lists.
3. The method of claim 1 , wherein the buffer manager is coupled to an enqueue processor operable for enqueuing the set of tokens of data into the allocated addresses of the more than two parallel linked memory lists, and is also coupled to a dequeue module operable for dequeuing the set of tokens of data from the allocated addresses of the more than two parallel linked memory lists.
4. The method of claim 3 , further comprising receiving requests from the enqueue processor to enqueue the more than two tokens of data, wherein the more than two tokens of data have addresses linked by pointers across the more than two parallel linked memory lists.
5. The method of claim 3 , further comprising receiving requests from the dequeue module to dequeue the more than two tokens of data, wherein the more than two tokens of data have addresses linked by pointers across the more than two parallel linked memory lists.
6. The method of claim 1 , further comprising populating the more than two parallel linked memory lists for the additional address allocations according to address availability.
7. The method of claim 6 , wherein said populating is performed in a round robin manner consecutively across each of the distinct parallel linked memory lists until all the requested addresses are allocated.
8. A system, comprising:
a memory buffer; and
a buffer manager coupled to the memory buffer, the buffer manager configured to:
receive a request for addresses and pointers for addresses allocated by the buffer manager, for storing a set of tokens of data from a queue selected from a plurality of queues, wherein the set of tokens of data comprises more than two tokens of data;
access a memory list, and generate the addresses and the pointers to allocated addresses in the memory list, wherein the memory list comprises more than two parallel linked memory lists;
write the pointers for the allocated addresses into the memory list to form a set of more than two linked memory locations, wherein each memory location of the set of more than two linked memory locations is allocated in a distinct parallel linked memory list in the more than two parallel linked memory lists, wherein the pointers externally link together each memory location of the set of more than two linked memory locations, and wherein each of the more than two parallel linked memory lists is divided into more than two memory locations; and
migrate to another set of more than two linked memory locations for additional address allocations upon receipt of another set of tokens of data from the queue, and generate additional pointers linking together memory locations of the other set of more than two linked memory locations.
9. The system of claim 8 , wherein the more than two parallel linked memory lists comprise a first memory list, a second memory list, a third memory list, and a fourth memory list, linked in parallel.
10. The system of claim 8 , wherein more than two allocated addresses of the set of tokens of data are linked by tail pointers and head pointers across the more than two parallel linked memory lists.
11. The system of claim 8 , further comprising an enqueue processor configured to: enqueue the set of tokens of data into the allocated addresses of the more than two parallel linked memory lists, and generate requests to the buffer manager for enqueuing the more than two tokens of data; and wherein the more than two tokens of data have addresses linked by pointers across the more than two parallel linked memory lists.
12. The system of claim 8 , further comprising a dequeue module configured to: dequeue the set of tokens of data from the allocated addresses of the more than two parallel linked memory lists, and generate requests to the buffer manager for dequeuing the more than two tokens of data; and wherein the more than two tokens of data have addresses linked by pointers across the more than two parallel linked memory lists.
13. The system of claim 8 , wherein the more than two parallel linked memory lists for the additional address allocations are dynamically populated according to address availability.
14. The system of claim 13 , wherein the more than two parallel linked memory lists are populated in a round robin manner consecutively across each of the distinct parallel linked memory lists until all the requested addresses are allocated.
15. A data processing system, comprising:
at least one processor operable for enqueuing a set of tokens of data into a memory list and for dequeuing the set of tokens of data from the allocated addresses of the parallel linked memory lists, wherein the set of tokens of data comprises more than two tokens of data, and Wherein the memory list comprises more than two parallel linked memory lists; and
a buffer manager coupled to the at least one processor, the buffer manager operable for performing a method to queue data to a memory buffer, the method comprising:
receiving a request for addresses and pointers for addresses allocated by the buffer manager, for storing the set of tokens of data;
accessing the memory list, and generating the addresses and the pointers to allocated addresses in the memory list;
writing the pointers for the allocated addresses into the memory list to form a set of more than two linked memory locations, wherein each memory location of the set of more than two linked memory locations is allocated in a distinct parallel linked memory list in the more than two parallel linked memory lists, wherein the pointers externally link together each memory location of the set of more than two linked memory locations, and wherein each of the more than two parallel linked memory lists is divided into more than two memory locations; and
migrating to another set of more than two linked memory locations for additional address allocations upon receipt of another set of tokens of data, and generating additional pointers linking together memory locations of the other set of more than two linked memory locations.
16. The data processing system of claim 15 , wherein the more than two parallel linked memory lists comprise a first memory list, a second memory list, a third memory list, and a fourth memory list, linked in parallel.
17. The data processing system of claim 15 , wherein more than two allocated addresses of the set of tokens of data are linked by tail pointers and head pointers across the more than two parallel linked memory lists.
18. The data processing system of claim 15 , further comprising an enqueue processor configured to: enqueue the set of tokens of data into the allocated addresses of the more than two parallel linked memory lists, and generate requests to the buffer manager for enqueuing the more than two tokens of data; and wherein the more than two tokens of data have addresses linked by pointers across the more than two parallel linked memory lists.
19. The data processing system of claim 15 , further comprising a dequeue module configured to: dequeue the set of tokens of data from the allocated addresses of the more than two parallel linked memory lists, and generate requests to the buffer manager for dequeuing the more than two tokens of data; and wherein the more than two tokens of data have addresses linked by pointers across the more than two parallel linked memory lists.
20. The data processing system of claim 15 , wherein the more than two parallel linked memory lists for the additional address allocations are dynamically populated according to address availability, and wherein the more than two parallel linked memory lists are populated in a round robin manner consecutively across each of the distinct parallel linked memory lists until all the requested addresses are allocated.