Nonvolatile semiconductor memory device and method for manufacturing same
According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.
1. A nonvolatile semiconductor memory device comprising:
a plurality of first memory cells stacked in a first direction and electrically connected in series, the plurality of first memory cells including:
a first semiconductor body extending in the first direction, the first semiconductor body having a first tubular structure;
a plurality of first floating electrodes provided on a side surface of the first semiconductor body via a first insulating layer, the first floating electrodes being stacked in the first direction; and
a plurality of first conductive layers stacked in the first direction, one of the first conductive layers being provided on a side surface of one of the first floating electrodes via a second insulating layer;
a first member provided inside the first semiconductor body, the first member having a columnar structure surrounded by the first tubular structure; and
a first select transistor including a first select gate electrode and a second semiconductor body extending in the first direction and connected to one end of the first semiconductor body,
the second semiconductor body being formed directly on the first semiconductor body and the first member and not overlapping with the first conductive layers when projected from the first direction,
wherein the first select gate electrode overlaps with the first floating electrodes and the first conductive layers when projected from the first direction.
2. The device according to claim 1 , wherein the first conductive layers include silicon.
3. The device according to claim 1 , wherein the first member includes silicon oxide.
4. The device according to claim 1 , wherein each of the first floating electrodes has a ring shape.
5. The device according to claim 1 , further comprising:
a plurality of second memory cells stacked in the first direction and electrically connected in series, the second memory cells being provided beside the plurality of first memory cells, the plurality of second memory cells including:
a third semiconductor body provided beside the first semiconductor body and extending in the first direction, the third semiconductor body having a second tubular structure;
a plurality of second floating electrodes provided on a side surface of the third semiconductor body via a third insulating layer; and
a plurality of second conductive layers stacked in the first direction, one of the second conductive layers being provided on a side surface of one of the second floating electrodes via a fourth insulating layer;
a second member provided inside the third semiconductor body, the second member having a columnar structure surrounded by the second tubular structure; and
a second select transistor including a second select gate electrode and a fourth semiconductor body extending in the first direction and connected to one end of the third semiconductor body,
the fourth semiconductor body being formed directly on the third semiconductor body and the second member and not overlapping with the second conductive layers when projected from the first direction.
6. The device according to claim 5 , wherein the first and second conductive layers include silicon.
7. The device according to claim 5 , wherein the first and second members include silicon oxide.
8. The device according to claim 5 , wherein each of the first and second floating electrodes has a ring shape.
9. The device according to claim 5 , wherein the second select gate electrode overlaps with the second floating electrodes and the second conductive layers when projected from the first direction.
10. The device according to claim 5 , further comprising:
a connection member connected to the other end of the first semiconductor body and the other end of the third semiconductor body, the connection member being formed of a conductor in substance.
11. The device according to claim 10 , wherein the connection member includes metal silicide.